Lines Matching refs:MIU_BUS
126 #define MIU_BUS (4) macro
690 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_LoadFW()
4577 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_SetVQ()
4605 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4609 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4613 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4617 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
5085 … REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5087 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5089 …REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5092 …REG32_W(&_RegCtrl->Str2mi_head2pvr1, (phyMiuOffsetPvrBuf1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetBuf()
5094 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetBuf()
5096 … REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetBuf()
5103 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5105 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5107 …REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MAS… in HAL_PVR_SetBuf()
5110 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (phyMiuOffsetPvrBuf1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5112 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5114 … REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (phyMiuOffsetPvrBuf1 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
5121 … REG32_W(&(_RegCtrl2->CFG_17_18), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD); in HAL_PVR_SetBuf()
5123 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0 >> MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL); in HAL_PVR_SetBuf()
5125 … REG32_W(&(_RegCtrl2->CFG_19_1A), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_19_1A_PVR3_STR2MI_MID); in HAL_PVR_SetBuf()
5128 … REG32_W(&(_RegCtrl2->CFG_1D_1E), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2); in HAL_PVR_SetBuf()
5130 … REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1 >> MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2); in HAL_PVR_SetBuf()
5132 … REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetBuf()
5139 … REG32_W(&(_RegCtrl2->CFG_24_25), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD); in HAL_PVR_SetBuf()
5141 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL); in HAL_PVR_SetBuf()
5143 … REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetBuf()
5146 … REG32_W(&(_RegCtrl2->CFG_2A_2B), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2); in HAL_PVR_SetBuf()
5148 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2); in HAL_PVR_SetBuf()
5150 … REG32_W(&(_RegCtrl2->CFG_2C_2D), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2C_2D_PVR4_STR2MI_MID2); in HAL_PVR_SetBuf()
5165 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5168 … REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5172 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5175 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5180 REG32_W(&(_RegCtrl2->CFG_17_18), (u32StartAddr0>>MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD); in HAL_PVR_SetStr2Miu_StartAddr()
5183 … REG32_W(&(_RegCtrl2->CFG_1D_1E), (u32StartAddr1>>MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2); in HAL_PVR_SetStr2Miu_StartAddr()
5187 REG32_W(&(_RegCtrl2->CFG_24_25), (u32StartAddr0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD); in HAL_PVR_SetStr2Miu_StartAddr()
5190 … REG32_W(&(_RegCtrl2->CFG_2A_2B), (u32StartAddr1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2); in HAL_PVR_SetStr2Miu_StartAddr()
5240 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5243 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5247 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5250 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5254 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0>>MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL); in HAL_PVR_SetStr2Miu_EndAddr()
5257 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1>>MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2); in HAL_PVR_SetStr2Miu_EndAddr()
5261 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL); in HAL_PVR_SetStr2Miu_EndAddr()
5264 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2); in HAL_PVR_SetStr2Miu_EndAddr()
5276 return (REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS); in HAL_PVR_GetWritePtr()
5279 return (REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS); in HAL_PVR_GetWritePtr()
5282 return (REG32_R(&(_RegCtrl2->CFG_66_67)) << MIU_BUS); in HAL_PVR_GetWritePtr()
5285 return (REG32_R(&(_RegCtrl2->CFG_68_69)) << MIU_BUS); in HAL_PVR_GetWritePtr()
6729 … REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK)); in HAL_TSP_OR_Address_Protect()
6730 … REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK)); in HAL_TSP_OR_Address_Protect()
6755 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_DMAW_BND_MASK); in HAL_TSP_SEC_Address_Protect()
6756 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_DMAW_BND_MASK); in HAL_TSP_SEC_Address_Protect()
6826 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_PVR_MASK); in HAL_TSP_PVR_Address_Protect()
6827 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_PVR_MASK); in HAL_TSP_PVR_Address_Protect()
6905 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK); in HAL_TSP_FILEIN_Address_Protect()
6906 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK); in HAL_TSP_FILEIN_Address_Protect()
6972 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK); in HAL_TSP_MMFI_Address_Protect()
6973 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK); in HAL_TSP_MMFI_Address_Protect()