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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halTSP_tee.c
97 // @brief Transport Stream Processer (TSP) HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #include "regTSP_tee.h"
101 #include "halTSP_tee.h"
102
103 //--------------------------------------------------------------------------------------------------
104 // Driver Compiler Option
105 //--------------------------------------------------------------------------------------------------
106
107 //--------------------------------------------------------------------------------------------------
108 // TSP Hardware Abstraction Layer
109 //--------------------------------------------------------------------------------------------------
110 static MS_VIRT _virtRegBase = 0;
111
112 //--------------------------------------------------------------------------------------------------
113 // Macro of bit operations
114 //--------------------------------------------------------------------------------------------------
115 #define TSP_TSP0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2A00 + ((addr)<<2))))
116 #define TSP_TSP1_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x2C00 + ((addr)<<2))))
117 #define TSP_MMFI_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3800 + ((addr)<<2))))
118 #define TSP_TSP3_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0xE0400 + ((addr)<<2))))
119
120 //--------------------------------------------------------------------------------------------------
121 // Forward declaration
122 //--------------------------------------------------------------------------------------------------
123
124 //--------------------------------------------------------------------------------------------------
125 // Implementation
126 //--------------------------------------------------------------------------------------------------
HAL_TSP_Tee_SetBank(MS_VIRT virtBankAddr)127 MS_BOOL HAL_TSP_Tee_SetBank(MS_VIRT virtBankAddr)
128 {
129 _virtRegBase = virtBankAddr;
130
131 return TRUE;
132 }
133
HAL_TSP_Tee_Set_FWBuf(MS_PHY phyAddr,MS_U32 u32Size)134 MS_BOOL HAL_TSP_Tee_Set_FWBuf(MS_PHY phyAddr, MS_U32 u32Size)
135 {
136 MS_U32 u32FwAddr = ((MS_U32)phyAddr >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT;
137 MS_U32 u32FwSize = TSP_QMEM_SIZES;
138
139 //printf("[%s][%d] u32FwAddr %x, u32FwSize %x \n", __FUNCTION__, __LINE__, (int)u32FwAddr, (int)u32FwSize);
140
141 TSP_TSP0_REG(REG_TSP0_FW_DMA_ADDR_L) = ((MS_U16)u32FwAddr) & 0xFFFF;
142 TSP_TSP1_REG(REG_TSP1_FW_DMA_ADDR_H) = (MS_U16)(u32FwAddr >> 16) & TSP_FW_DMA_ADDR_H_MASK;
143 TSP_TSP0_REG(REG_TSP0_FW_DMA_NUM) = (MS_U16)u32FwSize;
144
145 //lock down register
146 TSP_TSP1_REG(REG_TSP1_ONEWAY) = TSP_TSP1_REG(REG_TSP1_ONEWAY) | TSP_FW_ONEWAY;
147
148 return TRUE;
149 }
150
HAL_TSP_Tee_Set_VQBuf(MS_PHY phyAddr,MS_U32 u32Size)151 MS_BOOL HAL_TSP_Tee_Set_VQBuf(MS_PHY phyAddr, MS_U32 u32Size)
152 {
153 MS_U32 u32VQSize = 0, u32UnitSize = 0;
154 MS_PHY phyVQBufStart = phyAddr, phyMiuAddr = 0;
155 MS_U8 u8ii = 0;
156
157 u32VQSize = ((u32Size >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment
158 u32UnitSize = u32VQSize / TSP_VQ_PITCH;
159
160 //printf("[%s][%d] phyAddr %x, u32Size %x \n", __FUNCTION__, __LINE__, (int)phyAddr, (int)u32Size);
161 //printf("[%s][%d] u32VQSize %x, u32UnitSize %x \n", __FUNCTION__, __LINE__, (int)u32VQSize, (int)u32UnitSize);
162 for(u8ii = 0; u8ii < TSP_VQ_NUM; u8ii++)
163 {
164 phyMiuAddr = phyVQBufStart >> MIU_BUS;
165 if(u8ii == 0)
166 {
167 TSP_TSP1_REG(REG_TSP1_VQ0_BASE_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
168 TSP_TSP1_REG(REG_TSP1_VQ0_BASE_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
169 TSP_TSP1_REG(REG_TSP1_VQ0_SIZE) = (MS_U16)(u32UnitSize & 0xFFFF);
170 }
171 else if(u8ii == 1)
172 {
173 TSP_TSP1_REG(REG_TSP1_VQ1_BASE_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
174 TSP_TSP1_REG(REG_TSP1_VQ1_BASE_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
175 TSP_TSP1_REG(REG_TSP1_VQ1_SIZE) = (MS_U16)(u32UnitSize & 0xFFFF);
176 }
177 else if(u8ii == 2)
178 {
179 TSP_TSP1_REG(REG_TSP1_VQ2_BASE_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
180 TSP_TSP1_REG(REG_TSP1_VQ2_BASE_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
181 TSP_TSP1_REG(REG_TSP1_VQ2_SIZE) = (MS_U16)(u32UnitSize & 0xFFFF);
182 }
183
184 else if(u8ii == 3)
185 {
186 TSP_TSP1_REG(REG_TSP1_VQ3_BASE_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
187 TSP_TSP1_REG(REG_TSP1_VQ3_BASE_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
188 TSP_TSP1_REG(REG_TSP1_VQ3_SIZE) = (MS_U16)(u32UnitSize & 0xFFFF);
189 }
190 phyVQBufStart += u32VQSize;
191 }
192
193 return TRUE;
194
195 }
196
HAL_TSP_Tee_Set_PvrBuf(MS_U8 u8PvrId,MS_PHY phyAddr0,MS_U32 u32Size0,MS_PHY phyAddr1,MS_U32 u32Size1)197 MS_BOOL HAL_TSP_Tee_Set_PvrBuf(MS_U8 u8PvrId, MS_PHY phyAddr0, MS_U32 u32Size0, MS_PHY phyAddr1, MS_U32 u32Size1)
198 {
199 MS_PHY phyEnd = phyAddr0 + u32Size0;
200 MS_PHY phyMiuAddr = 0;
201
202 if(u8PvrId == 0)
203 {
204 phyMiuAddr = phyAddr0 >> MIU_BUS;
205 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
206 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
207 phyMiuAddr = phyEnd >> MIU_BUS;
208 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
209 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
210 phyEnd = phyAddr1 + u32Size1;
211 phyMiuAddr = phyAddr1 >> MIU_BUS;
212 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
213 TSP_TSP0_REG(REG_TSP0_PVR1_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
214 phyMiuAddr = phyEnd >> MIU_BUS;
215 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
216 TSP_TSP0_REG(REG_TSP0_PVR1_TAIL2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
217 }
218 else if(u8PvrId == 1)
219 {
220 phyMiuAddr = phyAddr0 >> MIU_BUS;
221 TSP_TSP0_REG(REG_TSP0_PVR2_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
222 TSP_TSP0_REG(REG_TSP0_PVR2_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
223 phyMiuAddr = phyEnd >> MIU_BUS;
224 TSP_TSP0_REG(REG_TSP0_PVR2_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
225 TSP_TSP0_REG(REG_TSP0_PVR2_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
226 phyEnd = phyAddr1 + u32Size1;
227 phyMiuAddr = phyAddr1 >> MIU_BUS;
228 TSP_TSP0_REG(REG_TSP0_PVR2_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
229 TSP_TSP0_REG(REG_TSP0_PVR2_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
230 phyMiuAddr = phyEnd >> MIU_BUS;
231 TSP_TSP0_REG(REG_TSP0_PVR2_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
232 TSP_TSP0_REG(REG_TSP0_PVR2_TAIL2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
233 }
234 else if(u8PvrId == 2)
235 {
236 phyMiuAddr = phyAddr0 >> MIU_BUS;
237 TSP_TSP3_REG(REG_TSP3_PVR3_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
238 TSP_TSP3_REG(REG_TSP3_PVR3_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
239 phyMiuAddr = phyEnd >> MIU_BUS;
240 TSP_TSP3_REG(REG_TSP3_PVR3_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
241 TSP_TSP3_REG(REG_TSP3_PVR3_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
242 phyEnd = phyAddr1 + u32Size1;
243 phyMiuAddr = phyAddr1 >> MIU_BUS;
244 TSP_TSP3_REG(REG_TSP3_PVR3_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
245 TSP_TSP3_REG(REG_TSP3_PVR3_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
246 phyMiuAddr = phyEnd >> MIU_BUS;
247 TSP_TSP3_REG(REG_TSP3_PVR3_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
248 TSP_TSP3_REG(REG_TSP3_PVR3_TAIL2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
249 }
250 else if(u8PvrId == 3)
251 {
252 phyMiuAddr = phyAddr0 >> MIU_BUS;
253 TSP_TSP3_REG(REG_TSP3_PVR4_HEAD1_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
254 TSP_TSP3_REG(REG_TSP3_PVR4_HEAD1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
255 phyMiuAddr = phyEnd >> MIU_BUS;
256 TSP_TSP3_REG(REG_TSP3_PVR4_TAIL1_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
257 TSP_TSP3_REG(REG_TSP3_PVR4_TAIL1_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
258 phyEnd = phyAddr1 + u32Size1;
259 phyMiuAddr = phyAddr1 >> MIU_BUS;
260 TSP_TSP3_REG(REG_TSP3_PVR4_HEAD2_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
261 TSP_TSP3_REG(REG_TSP3_PVR4_HEAD2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
262 phyMiuAddr = phyEnd >> MIU_BUS;
263 TSP_TSP3_REG(REG_TSP3_PVR4_TAIL2_L) = (MS_U16)(phyMiuAddr & 0xFFFF);
264 TSP_TSP3_REG(REG_TSP3_PVR4_TAIL2_H) = (MS_U16)((phyMiuAddr >> 16) & 0xFFFF);
265 }
266 else
267 {
268 return FALSE;
269 }
270
271 return TRUE;
272 }
273
HAL_TSP_Tee_Get_PVRWriteAddr(MS_U8 u8PvrId,MS_PHY * pphyAddr)274 MS_BOOL HAL_TSP_Tee_Get_PVRWriteAddr(MS_U8 u8PvrId, MS_PHY *pphyAddr)
275 {
276 MS_U16 u16addr = 0, u16addr1 = 0;
277
278 *pphyAddr = 0;
279
280 if(u8PvrId >= TSP_PVR_ENG_NUM)
281 return FALSE;
282
283 if(u8PvrId == 0)
284 {
285 u16addr = TSP_TSP0_REG(REG_TSP0_PVR1_MID1_L);
286 u16addr1 = TSP_TSP0_REG(REG_TSP0_PVR1_MID1_H);
287 *pphyAddr = (((MS_U32)u16addr) & 0xFFFF) + ((((MS_U32)u16addr1) << 16) & 0xFFFF0000);
288 *pphyAddr <<= MIU_BUS;
289 }
290 else if(u8PvrId == 1)
291 {
292 u16addr = TSP_TSP0_REG(REG_TSP0_PVR2_MID1_L);
293 u16addr1 = TSP_TSP0_REG(REG_TSP0_PVR2_MID1_H);
294 *pphyAddr = (((MS_U32)u16addr) & 0xFFFF) + ((((MS_U32)u16addr1) << 16) & 0xFFFF0000);
295 *pphyAddr <<= MIU_BUS;
296 }
297
298 else if(u8PvrId == 2)
299 {
300 u16addr = TSP_TSP3_REG(REG_TSP3_PVR3_MID1_L);
301 u16addr1 = TSP_TSP3_REG(REG_TSP3_PVR3_MID1_H);
302 *pphyAddr = (((MS_U32)u16addr) & 0xFFFF) + ((((MS_U32)u16addr1) << 16) & 0xFFFF0000);
303 *pphyAddr <<= MIU_BUS;
304 }
305 else if(u8PvrId == 3)
306 {
307 u16addr = TSP_TSP3_REG(REG_TSP3_PVR4_MID1_L);
308 u16addr1 = TSP_TSP3_REG(REG_TSP3_PVR4_MID1_H);
309 *pphyAddr = (((MS_U32)u16addr) & 0xFFFF) + ((((MS_U32)u16addr1) << 16) & 0xFFFF0000);
310 *pphyAddr <<= MIU_BUS;
311 }
312 else
313 {
314 return FALSE;
315 }
316
317
318 return TRUE;
319 }
320
HAL_TSP_Tee_FilePath2Tsif_Mapping(MS_U8 u8FileEng)321 MS_U32 HAL_TSP_Tee_FilePath2Tsif_Mapping(MS_U8 u8FileEng)
322 {
323 switch (u8FileEng)
324 {
325 case 0:
326 return TSP_TSIF1;
327 case 1:
328 return TSP_TSIF3;
329 case 2:
330 return TSP_TSIF0;
331 case 3:
332 return TSP_TSIF2;
333 default:
334 return 0xFF;
335 }
336 }
337
HAL_TSP_Tee_Set_FileinBuf(MS_U8 u8EngId,MS_PHY phyAddr,MS_U32 u32Size)338 MS_BOOL HAL_TSP_Tee_Set_FileinBuf(MS_U8 u8EngId, MS_PHY phyAddr, MS_U32 u32Size)
339 {
340 MS_U32 u32Tsif = HAL_TSP_Tee_FilePath2Tsif_Mapping(u8EngId);
341
342 switch(u32Tsif)
343 {
344 case 0:
345 TSP_TSP0_REG(REG_TSP0_FILE_SIZE_L) = (MS_U16)(u32Size & 0xFFFF);
346 TSP_TSP0_REG(REG_TSP0_FILE_SIZE_H) = (MS_U16)((u32Size >> 16) & 0xFFFF);
347 TSP_TSP0_REG(REG_TSP0_FILE_ADDR_L) = (MS_U16)(phyAddr & 0xFFFF);
348 TSP_TSP0_REG(REG_TSP0_FILE_ADDR_H) = (MS_U16)((phyAddr >> 16) & 0xFFFF);
349 break;
350 case 1:
351 TSP_TSP3_REG(REG_TSP3_FILE1_SIZE_L) = (MS_U16)(u32Size & 0xFFFF);
352 TSP_TSP3_REG(REG_TSP3_FILE1_SIZE_H) = (MS_U16)((u32Size >> 16) & 0xFFFF);
353 TSP_TSP3_REG(REG_TSP3_FILE1_ADDR_L) = (MS_U16)(phyAddr & 0xFFFF);
354 TSP_TSP3_REG(REG_TSP3_FILE1_ADDR_H) = (MS_U16)((phyAddr >> 16) & 0xFFFF);
355 break;
356 case 2:
357 TSP_TSP3_REG(REG_TSP3_FILE2_SIZE_L) = (MS_U16)(u32Size & 0xFFFF);
358 TSP_TSP3_REG(REG_TSP3_FILE2_SIZE_H) = (MS_U16)((u32Size >> 16) & 0xFFFF);
359 TSP_TSP3_REG(REG_TSP3_FILE2_ADDR_L) = (MS_U16)(phyAddr & 0xFFFF);
360 TSP_TSP3_REG(REG_TSP3_FILE2_ADDR_H) = (MS_U16)((phyAddr >> 16) & 0xFFFF);
361 break;
362 case 3:
363 TSP_TSP3_REG(REG_TSP3_FILE3_SIZE_L) = (MS_U16)(u32Size & 0xFFFF);
364 TSP_TSP3_REG(REG_TSP3_FILE3_SIZE_H) = (MS_U16)((u32Size >> 16) & 0xFFFF);
365 TSP_TSP3_REG(REG_TSP3_FILE3_ADDR_L) = (MS_U16)(phyAddr & 0xFFFF);
366 TSP_TSP3_REG(REG_TSP3_FILE3_ADDR_H) = (MS_U16)((phyAddr >> 16) & 0xFFFF);
367 break;
368 default:
369 return FALSE;
370 }
371
372 return TRUE;
373 }
374
HAL_TSP_Tee_Set_MMFIBuf(MS_U8 u8Id,MS_PHY phyAddr,MS_U32 u32Size)375 MS_BOOL HAL_TSP_Tee_Set_MMFIBuf(MS_U8 u8Id, MS_PHY phyAddr, MS_U32 u32Size)
376 {
377 switch(u8Id)
378 {
379 case 0:
380 TSP_MMFI_REG(REG_MMFI_FILE_ADDR_L) = (MS_U16)(phyAddr & 0xFFFF);
381 TSP_MMFI_REG(REG_MMFI_FILE_ADDR_H) = (MS_U16)((phyAddr >> 16) & 0xFFFF);
382 TSP_MMFI_REG(REG_MMFI_FILE_SIZE_L) = (MS_U16)(u32Size & 0xFFFF);
383 TSP_MMFI_REG(REG_MMFI_FILE_SIZE_H) = (MS_U16)((u32Size >> 16) & 0xFFFF);
384 break;
385 case 1:
386 TSP_MMFI_REG(REG_MMFI1_FILE_ADDR_L) = (MS_U16)(phyAddr & 0xFFFF);
387 TSP_MMFI_REG(REG_MMFI1_FILE_ADDR_H) = (MS_U16)((phyAddr >> 16) & 0xFFFF);
388 TSP_MMFI_REG(REG_MMFI1_FILE_SIZE_L) = (MS_U16)(u32Size & 0xFFFF);
389 TSP_MMFI_REG(REG_MMFI1_FILE_SIZE_H) = (MS_U16)((u32Size >> 16) & 0xFFFF);
390 break;
391 default:
392 return FALSE;
393 }
394
395 return TRUE;
396 }
397