118 #define MIU_BUS                     4UL  macro
1473 …TspCtrl[0].TsRec_Head, ((MS_U32)((phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A…  in HAL_TSP_PVR_SetBuffer()
1474 …(&_TspCtrl[0].TsRec_Tail, ((MS_U32)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)) & TSP_STR2MI2_A…  in HAL_TSP_PVR_SetBuffer()
1484 …REG16_T(ADDR_PVR_HEAD20)=   (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_P…  in HAL_TSP_PVR_SetBuffer()
1485 …REG16_T(ADDR_PVR_HEAD21)=   (MS_U16)(((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & T…  in HAL_TSP_PVR_SetBuffer()
1486 …REG16_T(ADDR_PVR_TAIL20)=   (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & (TSP_HW_PVR_…  in HAL_TSP_PVR_SetBuffer()
1487 …REG16_T(ADDR_PVR_TAIL21)=   (MS_U16)(((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16UL)) & TSP_…  in HAL_TSP_PVR_SetBuffer()
1500 …[0].Str2mi_head1_pvr2, (MS_U32)(((phyBufStart0-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD…  in HAL_TSP_PVR_SetBuffer()
1501 …trl[0].Str2mi_tail1_pvr2, (MS_U32)(((phyBufEnd-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD…  in HAL_TSP_PVR_SetBuffer()
1502 …[0].Str2mi_head2_pvr2, (MS_U32)(((phyBufStart1-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD…  in HAL_TSP_PVR_SetBuffer()
1504 …trl[0].Str2mi_tail2_pvr2, (MS_U32)(((phyBufEnd-_phyPVRBufMiuOffset[1])>> MIU_BUS) & TSP_STR2MI2_AD…  in HAL_TSP_PVR_SetBuffer()
1712     return ((((MS_PHY)u32value) << MIU_BUS) + _phyPVRBufMiuOffset[u8PVRId]);  in HAL_TSP_PVR_GetBufWrite()
2383         *((MS_U32*)pData) = (1L << (MIU_BUS+TSP_DNLD_ADDR_ALI_SHIFT));  in HAL_TSP_GetCap()
2388         *((MS_U32*)pData) = (1L << MIU_BUS);  in HAL_TSP_GetCap()
2482 …u32DnldCtrl  =      (MS_U32)((((phyFwAddrPhys-_phyOrLoadMiuOffset) >> MIU_BUS) >> TSP_DNLD_ADDR_AL…  in _HAL_TSP_FW_load()
2483 …u32DnldCtrl1 =      (MS_U32)(((((phyFwAddrPhys-_phyOrLoadMiuOffset) >> MIU_BUS) >> TSP_DNLD_ADDR_A…  in _HAL_TSP_FW_load()
3114             phyStartAddr += (1UL << MIU_BUS);  in HAL_TSP_OrzWriteProtect_Enable()
3116         lbnd  = (MS_U32)(((phyStartAddr-phyMiuOffset) >>  MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK);  in HAL_TSP_OrzWriteProtect_Enable()
3117         ubnd  = (MS_U32)(((phyEndAddr-phyMiuOffset) >>  MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK);  in HAL_TSP_OrzWriteProtect_Enable()
4254 …*pphyReadAddr = ((MS_PHY)_HAL_REG32_R(&_TspCtrl[0].TsFileIn_RPtr) << MIU_BUS) + _phyFIBufMiuOffset;  in HAL_TSP_GetFilinReadAddr()
4797     _HAL_REG32_W(pReg, (MS_U32)((phyBaseAddr-phyVqBufOffset) >> MIU_BUS));  in HAL_TSP_SetVQBuffer()
5027                 pphyStartAddr[u8ii] += (1UL << MIU_BUS);  in HAL_TSP_WriteProtect_Enable()
5030 …Ctrl[0].DMAW_LBND0, ((MS_U32)(pphyStartAddr[0]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[0]))) >> MIU_BUS);  in HAL_TSP_WriteProtect_Enable()
5031 …_TspCtrl[0].DMAW_UBND0, ((MS_U32)(pphyEndAddr[0]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[0]))) >> MIU_BUS);  in HAL_TSP_WriteProtect_Enable()
5032 …Ctrl[0].DMAW_LBND1, ((MS_U32)(pphyStartAddr[1]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[1]))) >> MIU_BUS);  in HAL_TSP_WriteProtect_Enable()
5033 …_TspCtrl[0].DMAW_UBND1, ((MS_U32)(pphyEndAddr[1]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[1]))) >> MIU_BUS);  in HAL_TSP_WriteProtect_Enable()
5034 …Ctrl[0].DMAW_LBND2, ((MS_U32)(pphyStartAddr[2]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[2]))) >> MIU_BUS);  in HAL_TSP_WriteProtect_Enable()
5035 …_TspCtrl[0].DMAW_UBND2, ((MS_U32)(pphyEndAddr[2]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[2]))) >> MIU_BUS);  in HAL_TSP_WriteProtect_Enable()
5036 …Ctrl[0].DMAW_LBND4, ((MS_U32)(pphyStartAddr[4]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[4]))) >> MIU_BUS);  in HAL_TSP_WriteProtect_Enable()
5037 …_TspCtrl[0].DMAW_UBND4, ((MS_U32)(pphyEndAddr[4]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[4]))) >> MIU_BUS);  in HAL_TSP_WriteProtect_Enable()