Lines Matching refs:MIU_BUS
113 #define MIU_BUS 4 macro
1477 _HAL_REG32_W(&_TspCtrl[0].TsRec_Head, (u32BufStart0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1478 _HAL_REG32_W(&_TspCtrl[0].TsRec_Tail, (u32BufEnd>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1488 …REG16_T(ADDR_PVR_HEAD20)= (u32BufStart1>> MIU_BUS) & (TSP_HW_PVR_BUF_HEAD20_MASK >> TSP_HW_PVR_B… in HAL_TSP_PVR_SetBuffer()
1489 REG16_T(ADDR_PVR_HEAD21)= (u32BufStart1>> (MIU_BUS+ 16)) & TSP_HW_PVR_BUF_HEAD21_MASK; in HAL_TSP_PVR_SetBuffer()
1490 …REG16_T(ADDR_PVR_TAIL20)= (u32BufEnd>> MIU_BUS) & (TSP_HW_PVR_BUF_TAIL20_MASK >> TSP_HW_PVR_BUF_… in HAL_TSP_PVR_SetBuffer()
1491 REG16_T(ADDR_PVR_TAIL21)= (u32BufEnd>> (MIU_BUS+ 16)) & TSP_HW_PVR_BUF_TAIL21_MASK; in HAL_TSP_PVR_SetBuffer()
1503 … _HAL_REG32_W(&_TspCtrl[0].Str2mi_head1_pvr2, (u32BufStart0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1504 … _HAL_REG32_W(&_TspCtrl[0].Str2mi_tail1_pvr2, (u32BufEnd>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1505 … _HAL_REG32_W(&_TspCtrl[0].Str2mi_head2_pvr2, (u32BufStart1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1507 … _HAL_REG32_W(&_TspCtrl[0].Str2mi_tail2_pvr2, (u32BufEnd>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_TSP_PVR_SetBuffer()
1712 return (u32value << MIU_BUS); in HAL_TSP_PVR_GetBufWrite()
2297 *((MS_U32*)pData) = (1L << (MIU_BUS+TSP_DNLD_ADDR_ALI_SHIFT)); in HAL_TSP_GetCap()
2302 *((MS_U32*)pData) = (1L << MIU_BUS); in HAL_TSP_GetCap()
2395 … u32DnldCtrl = ((u32FwAddrPhys >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT) & TSP_DNLD_ADDR_MASK; in _HAL_TSP_FW_load()
2396 …u32DnldCtrl1 = (((u32FwAddrPhys >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT) >> 16) & TSP_DMA_RADD… in _HAL_TSP_FW_load()
2879 u32StartAddr += (1 << MIU_BUS); in HAL_TSP_OrzWriteProtect_Enable()
2881 lbnd = (u32StartAddr >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK; in HAL_TSP_OrzWriteProtect_Enable()
2882 ubnd = (u32EndAddr >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK; in HAL_TSP_OrzWriteProtect_Enable()
3724 *pu32ReadAddr = (_HAL_REG32_R(&_TspCtrl[0].TsFileIn_RPtr) << MIU_BUS); in HAL_TSP_GetFilinReadAddr()
4070 _HAL_REG32_W(pReg, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_SetVQBuffer()
4279 pu32StartAddr[u8ii] += (1 << MIU_BUS); in HAL_TSP_WriteProtect_Enable()
4282 _HAL_REG32_W(&_TspCtrl[0].DMAW_LBND0, pu32StartAddr[0] >> MIU_BUS); in HAL_TSP_WriteProtect_Enable()
4283 _HAL_REG32_W(&_TspCtrl[0].DMAW_UBND0, pu32EndAddr[0] >> MIU_BUS); in HAL_TSP_WriteProtect_Enable()
4284 _HAL_REG32_W(&_TspCtrl[0].DMAW_LBND1, pu32StartAddr[1] >> MIU_BUS); in HAL_TSP_WriteProtect_Enable()
4285 _HAL_REG32_W(&_TspCtrl[0].DMAW_UBND1, pu32EndAddr[1] >> MIU_BUS); in HAL_TSP_WriteProtect_Enable()
4286 _HAL_REG32_W(&_TspCtrl[0].DMAW_LBND2, pu32StartAddr[2] >> MIU_BUS); in HAL_TSP_WriteProtect_Enable()
4287 _HAL_REG32_W(&_TspCtrl[0].DMAW_UBND2, pu32EndAddr[2] >> MIU_BUS); in HAL_TSP_WriteProtect_Enable()
4288 _HAL_REG32_W(&_TspCtrl[0].DMAW_LBND4, pu32StartAddr[3] >> MIU_BUS); in HAL_TSP_WriteProtect_Enable()
4289 _HAL_REG32_W(&_TspCtrl[0].DMAW_UBND4, pu32EndAddr[3] >> MIU_BUS); in HAL_TSP_WriteProtect_Enable()