1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halPVR.c
20 // @brief PVR HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "halCHIP.h"
25 #include "regTSP.h"
26 #include "halTSP.h"
27 #include "drvSYS.h"
28
29 #ifdef CONFIG_MSTAR_CLKM
30 #include "drvCLKM.h"
31 #endif
32
33 #ifdef MSOS_TYPE_LINUX_KERNEL
34 #include <linux/string.h>
35 #else
36 #include <string.h>
37 #endif
38 //--------------------------------------------------------------------------------------------------
39 // Driver Compiler Option
40 //--------------------------------------------------------------------------------------------------
41 #define FPGA_TEST 1
42
43 //--------------------------------------------------------------------------------------------------
44 // TSP Hardware Abstraction Layer
45 //--------------------------------------------------------------------------------------------------
46 static MS_VIRT _u32RegBase = 0;
47
48 static REG_Ctrl *_RegCtrl = NULL; // TSP 0/1
49 static REG_TSP_MULTI_Ctrl *_RegTspMultiCtrl = NULL; // TSP_MULTI
50 static REG_TSP_MULTI_SYNC_Ctrl *_RegTspMultiSyncCtrl = NULL; // TSP_MULTI_SYNC_0 (0 ~ 3)
51 static REG_TSP_MULTI_SYNC_Ctrl *_RegTspMultiSyncCtrl_1 = NULL; // TSP_MULTI_SYNC_1 (4 ~ 6)
52 static REG_TSP_SRC_Ctrl *_RegTspSrcCtrl = NULL; // TSP_SRC
53 static REG_PATH_ENG_Ctrl *_RegPathCtrl = NULL; // Path
54 static REG_FILE_ENG_Ctrl *_RegFile0Ctrl = NULL; // File #0
55 static REG_FILE_ENG_Ctrl *_RegFile1Ctrl = NULL; // File #1
56 static REG_OTHER_Ctrl *_RegOtherCtrl = NULL; // Other/resample
57 static REG_TOP_Ctrl *_RegTopCtrl = NULL; // Top
58 static REG_AV_ENG_Ctrl *_RegAudioCtrl = NULL; // Audio
59 static REG_AV_ENG_Ctrl *_RegVideoCtrl = NULL; // Video
60 static REG_PVR_ENG_Ctrl *_RegPvrCtrl = NULL; // PVR (1~8)
61 static REG_PVR_ENG_Ctrl *_RegPvrCtrl_1 = NULL; // PVR (9~10)
62 static REG_STC_ENG_Ctrl *_RegStcCtrl = NULL; // STC
63 static REG_PCR_ENG_Ctrl *_RegPcrCtrl = NULL; // PCR
64 static REG_SPS_ENG_Ctrl *_RegSpsCtrl = NULL; // SPS (1~8)
65 static REG_SPS_ENG_Ctrl *_RegSpsCtrl_1 = NULL; // SPS (9~10)
66 static REG_SPD_ENG_Ctrl *_RegSpdCtrl = NULL; // SPD
67
68
69 // @F_TODO These parameters need to be combined with global variables in Utopia 2.0
70 static MS_U32 _u32PidFltReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
71 static MS_U32 _u32PidDstReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
72 static MS_U32 _u32PidDst2Reg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
73 static MS_U32 _u32SecReg[(TSP_SECFLT_NUM * ((sizeof(REG_SecFlt) - sizeof(((REG_SecFlt*)0)->_x54))/sizeof(TSP32)))];
74
75
76 //-------------------------------------------------------------------------------------------------
77 // Local Functions
78 //-------------------------------------------------------------------------------------------------
79 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value);
80
_delay(MS_U32 usec)81 static void _delay(MS_U32 usec)
82 {
83 MsOS_DelayTaskUs_Poll(usec);
84 }
85
REG32_R(REG32 * reg)86 static MS_U32 REG32_R(REG32 *reg)
87 {
88 MS_U32 value = 0;
89 value = (reg)->low;
90 value |= (reg)->high << 16;
91 return value;
92 }
93
94
REG16_R(REG16 * reg)95 static MS_U16 REG16_R(REG16 *reg)
96 {
97 MS_U16 value = 0;
98 value = (reg)->data;
99 return value;
100 }
101
102 static MS_BOOL _u32RegDump = 0;
103 static void _REG32_DUMP(REG32 * reg, MS_U32 value );
104 static void _REG16_DUMP(REG16 * reg, MS_U16 value);
105
106 #define REG32_W(reg, value) { (reg)->low = ((value) & 0x0000FFFF); \
107 (reg)->high = ((value) >> 16); \
108 if(_u32RegDump){_REG32_DUMP(reg, value);}}
109
110 #define REG16_W(reg, value) {(reg)->data = ((value) & 0x0000FFFF); \
111 if(_u32RegDump){_REG16_DUMP(reg, value);}}
112
113
114 #define _AND_(flag, bit) ((flag) & (bit) )
115
116 #define _SET_(flag, bit) ((flag) | (bit) )
117 #define _CLR_(flag, bit) ((flag) & (~(bit)))
118
119 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value))
120 #define REG32_SET(reg, value) REG32_W(reg, _SET_(REG32_R(reg), value))
121 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value))
122 #define REG32_CLR(reg, value) REG32_W(reg, _CLR_(REG32_R(reg), value))
123
124 #define REG16_MSK_W(reg, mask, value) REG16_W((reg), _CLR_(REG16_R(reg), (mask)) | _AND_((value), (mask)))
125 #define REG32_MSK_W(reg, mask, value) REG32_W((reg), _CLR_(REG32_R(reg), (mask)) | _AND_((value), (mask)))
126
127 #define MIU_BUS (4)
128
129
130 //-------------------------------------------------------------------------------------------------
131 // Debug Message
132 //-------------------------------------------------------------------------------------------------
133 typedef enum
134 {
135 E_HAL_TSP_DBG_LEVEL_NONE, // no debug message shown
136 E_HAL_TSP_DBG_LEVEL_ERR, // only shows error message that can't be recover
137 E_HAL_TSP_DBG_LEVEL_WARN, // error case can be recover, like retry
138 E_HAL_TSP_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
139 E_HAL_TSP_DBG_LEVEL_INFO, // information for internal parameter
140 E_HAL_TSP_DBG_LEVEL_FUNC, // Function trace and input parameter trace
141 E_HAL_TSP_DBG_LEVEL_TRACE, // debug trace
142 } EN_HAL_TSP_DBGMSG_LEVEL;
143
144 typedef enum
145 {
146 E_HAL_TSP_DBG_MODEL_NONE, // @temporarily , need to refine
147 E_HAL_TSP_DBG_MODEL_ALL,
148 } EN_HAL_TSP_DBGMSG_MODEL;
149
150 #define HAL_TSP_DBGMSG(_level,_model,_f) do {if(_u32TSPDbgLevel >= (_level)&&((_u32TSPDbgModel&_model)!=0)) (_f);} while(0)
151 static MS_U32 _u32TSPDbgLevel = E_HAL_TSP_DBG_LEVEL_ERR;
152 static MS_U32 _u32TSPDbgModel = E_HAL_TSP_DBG_MODEL_ALL;
153
154
155 //--------------------------------------------------------------------------------------------------
156 // Implementation
157 //--------------------------------------------------------------------------------------------------
TSP32_IdrW(TSP32 * preg,MS_U32 value)158 void TSP32_IdrW(TSP32 *preg, MS_U32 value)
159 {
160 MS_U32 tempDump = _u32RegDump;
161 if(_u32RegDump)
162 {
163 //test_chip_top.write_ind32('h00221004, 32'hffffffff); //indirect .... (address,data)
164 _u32RegDump = 0;
165 printf("test_chip_top.write_ind32(\'h%08lx, 32\'h%08lx);\n", (long unsigned int)preg, (long unsigned int)value);
166 }
167 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
168 REG32_W(&_RegCtrl->Idr_Write, value);
169 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_WRITE);
170 _u32RegDump = tempDump;
171 }
172
TSP32_IdrR(TSP32 * preg)173 MS_U32 TSP32_IdrR(TSP32 *preg)
174 {
175 MS_U32 tempDump = _u32RegDump;
176 if(_u32RegDump)
177 {
178 _u32RegDump = 0;
179 }
180 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
181 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_READ);
182 _u32RegDump = tempDump;
183 return REG32_R(&_RegCtrl->Idr_Read);
184 }
185
HAL_TSP_SetBank(MS_VIRT u32BankAddr)186 void HAL_TSP_SetBank(MS_VIRT u32BankAddr)
187 {
188 _u32RegBase = u32BankAddr;
189
190 _RegCtrl = (REG_Ctrl*) (u32BankAddr + 0x2A00UL); // TSP0/1 0x1015/0x1016
191 _RegPathCtrl = (REG_PATH_ENG_Ctrl*) (u32BankAddr + 0xC2000UL); // Path 0x1610
192 _RegFile0Ctrl = (REG_FILE_ENG_Ctrl*) (u32BankAddr + 0xC2200UL); // File0 0x1611
193 _RegFile1Ctrl = (REG_FILE_ENG_Ctrl*) (u32BankAddr + 0xC4E00UL); // File1 0x1627
194 _RegPvrCtrl_1 = (REG_PVR_ENG_Ctrl*) (u32BankAddr + 0xC5600UL); // PVR 9~10 0x162B
195 _RegSpsCtrl_1 = (REG_SPS_ENG_Ctrl*) (u32BankAddr + 0xC5800UL); // SPS 9~10 0x162C
196 _RegOtherCtrl = (REG_OTHER_Ctrl*) (u32BankAddr + 0xE0400UL); // Other 0x1702
197 _RegTopCtrl = (REG_TOP_Ctrl*) (u32BankAddr + 0xE0600UL); // Top 0x1703
198 _RegSpdCtrl = (REG_SPD_ENG_Ctrl*) (u32BankAddr + 0xE1800UL); // SPD 0x170C
199 _RegSpsCtrl = (REG_SPS_ENG_Ctrl*) (u32BankAddr + 0xE1A00UL); // SPS 1~8 0x170D
200
201 _RegAudioCtrl = (REG_AV_ENG_Ctrl*) (u32BankAddr + 0x400400UL); // Audio 0x3002
202 _RegVideoCtrl = (REG_AV_ENG_Ctrl*) (u32BankAddr + 0x400600UL); // Video 0x3003
203 _RegPvrCtrl = (REG_PVR_ENG_Ctrl*) (u32BankAddr + 0x401400UL); // PVR 1~8 0x300A ~ 0x300D
204 _RegStcCtrl = (REG_STC_ENG_Ctrl*) (u32BankAddr + 0x401C00UL); // STC 0x300E
205 _RegPcrCtrl = (REG_PCR_ENG_Ctrl*) (u32BankAddr + 0x401C80UL); // PCR 0x300E (offset: 0x20)
206 _RegTspMultiCtrl = (REG_TSP_MULTI_Ctrl*) (u32BankAddr + 0x402600UL); // TSP_MULTI 0x3013
207 _RegTspSrcCtrl = (REG_TSP_SRC_Ctrl*) (u32BankAddr + 0x402800UL); // TSP_SRC 0x3014
208 _RegTspMultiSyncCtrl = (REG_TSP_MULTI_SYNC_Ctrl*) (u32BankAddr + 0x402A00UL); // TSP_MULTI_SYNC_0 0x3015
209 _RegTspMultiSyncCtrl_1 = (REG_TSP_MULTI_SYNC_Ctrl*) (u32BankAddr + 0x404E00UL); // TSP_MULTI_SYNC_1 0x3027
210 }
211
HAL_TSP_RegDump(MS_BOOL bEnable)212 void HAL_TSP_RegDump(MS_BOOL bEnable)
213 {
214 _u32RegDump = bEnable;
215 }
216
217 #if 1
_REG32_DUMP(REG32 * reg,MS_U32 value)218 static void _REG32_DUMP(REG32* reg, MS_U32 value )
219 {
220 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7’h06 ....reg ,16’h400a ......
221 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7’h06 ....reg ,16’h400a ......
222 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
223 MS_U32 bank = ((MS_VIRT)(&(reg)->low) - _u32RegBase)>>(1+8);
224 MS_U32 addr_low = ((((MS_VIRT)(&(reg)->low) - _u32RegBase)>>1)&0xFF)>>1;
225 MS_U32 addr_high = ((((MS_VIRT)(&(reg)->high) - _u32RegBase)>>1)&0xFF)>>1;
226 MS_U32 val_low = (value) & 0x0000FFFF;
227 MS_U32 val_high = ((value) & 0xFFFF0000 )>>16;
228
229 if(bank == 0x15)
230 {
231 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
232 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
233 }
234 else if(bank == 0x16)
235 {
236 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
237 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
238 }
239 else if(bank == 0x38)
240 {
241 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
242 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
243 }
244 }
245
_REG16_DUMP(REG16 * reg,MS_U16 value)246 static void _REG16_DUMP(REG16* reg, MS_U16 value )
247 {
248 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7’h06 ....reg ,16’h400a ......
249 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7’h06 ....reg ,16’h400a ......
250 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
251 MS_U32 bank = ((MS_VIRT)(&(reg)) - _u32RegBase)>>(1+8);
252 MS_U32 addr = ((((MS_VIRT)(&(reg)) - _u32RegBase)>>1)&0xFF)>>1;
253 MS_U32 val = (value) & 0x0000FFFF;
254
255 if(bank == 0x15)
256 {
257 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
258 }
259 else if(bank == 0x16)
260 {
261 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
262 }
263 else if(bank == 0x38)
264 {
265 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
266 }
267 }
268 #endif
269
HAL_TSP_HwPatch(void)270 void HAL_TSP_HwPatch(void)
271 {
272 //For sram
273 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE);
274 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION);
275
276 // @F_TODO check these setting with Stephen
277 // TSP_HW_CFG4_WSTAT_CH_EN <--this is bit disable HW sync section buf id with section filter id
278 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WSTAT_CH_EN);
279
280 // Bad initial value of TSP_CTRL1
281 // Suppose Standby mode for TSP should NOT be enabled.
282 // Enabling TSP standby mode cause TSP section registers (SRAM in AEON) malfunction.
283 // Disable it by SW at this stage.
284 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY);
285
286 MS_U8 u8Idx = 0;
287
288 for(u8Idx = 0; u8Idx < TSP_PVRENG_NUM; u8Idx++)
289 {
290 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u8Idx < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
291 MS_U8 u8PvrEng = (u8Idx < E_TSP_PVR_PVRENG_8)? u8Idx : (u8Idx - E_TSP_PVR_PVRENG_8);
292
293 // enable PVR record to bypass header
294 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_RECORD_TS);
295
296 // record null packets for record-all case
297 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_DIS_NULL_PKT);
298
299 // Fixed PVR eng write pointer to next addr
300 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_PVR_WRITE_POINTER_TO_NEXT_ADDRESS_EN);
301
302 // skip FQ rush data
303 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_SKIP_PVR_RUSH_DATA);
304 }
305
306 for(u8Idx = 0; u8Idx < TSP_PCRFLT_NUM; u8Idx++)
307 {
308 // skip FQ rush data
309 REG16_SET(&_RegPcrCtrl[u8Idx].CFG_PCR_00, CFG_PCR_00_REG_SKIP_PVR_RUSH_DATA);
310 }
311
312 for(u8Idx = 0; u8Idx < E_TSP_HAL_CAP_VAL_AFIFO_NUM; u8Idx++)
313 {
314 REG16_SET(&_RegAudioCtrl[u8Idx].CFG_AV_00, (CFG_AV_00_REG_DUP_PKT_SKIP | CFG_AV_00_REG_PUSI_THREE_BYTE_MODE));
315 }
316
317 for(u8Idx = 0; u8Idx < E_TSP_HAL_CAP_VAL_VFIFO_NUM; u8Idx++)
318 {
319 REG16_SET(&_RegVideoCtrl[u8Idx].CFG_AV_00, (CFG_AV_00_REG_DUP_PKT_SKIP | CFG_AV_00_REG_PUSI_THREE_BYTE_MODE));
320 }
321
322 //Disable TSP_RM_OVF_GLITCH to fix that section A would occur overflow when section B occured overflow at first.
323 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN*/);
324
325 //If SEC CMP adopts pingpong mode (1 + 1 packets) , there is always 1 packet stayed in queue.
326 //For example , if it receive 100 packets , the last packet is not in section buffer.
327 //Set below bits can force SEC CMP processing SEC packet after receiving a complete 188 bytes.
328 REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC);
329 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_FIX_PINPON_SYNCP_IN);
330
331 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH);
332
333 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
334
335 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD);
336
337 for(u8Idx = 0; u8Idx < TSP_TSIF_NUM; u8Idx++)
338 {
339 REG16_SET(&_RegPathCtrl[u8Idx].CFG_PATH_08, CFG_PATH_08_REG_BLK_AF_SCRMB_BIT_TSP);
340
341 // Merge stream through FIQ ECO config
342 REG16_SET(&_RegPathCtrl[u8Idx].CFG_PATH_06, CFG_PATH_06_REG_ECO_TS_SYNC_OUT_DELAY);
343 REG16_SET(&_RegPathCtrl[u8Idx].CFG_PATH_06, CFG_PATH_06_REG_ECO_TS_SYNC_OUT_REVERSE_BLOCK);
344
345 // Fix filter null packet
346 REG16_SET(&_RegPathCtrl[u8Idx].CFG_PATH_06, CFG_PATH_06_REG_FIX_FILTER_NULL_PKT);
347 }
348
349 // Serial mode config
350 REG16_SET(&_RegCtrl->reg15b8, TSP_SERIAL_EXT_SYNC_1T);
351 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT);
352 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_VALID_FALLING_DETECT)
353
354 // Internal Sync Patch
355 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T);
356
357 for(u8Idx = 0; u8Idx < TSP_TSIF_NUM; u8Idx++)
358 {
359 REG_FILE_ENG_Ctrl *RegFileCtrl = (u8Idx < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
360 MS_U8 u8FileEng = (u8Idx < E_FILEENG_TSIF4)? u8Idx : (u8Idx - E_FILEENG_TSIF4);
361
362 // Chip after Kirin will lost data when byte timer enable and delay set to 0 setting this bit to fix this issue
363 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0A, CFG_FILE_0A_REG_FIX_192_TIMER_0_EN);
364
365 // Fix pass_pkt_timestamp will hang issue
366 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0A, CFG_FILE_0A_REG_INIT_STAMP_RSTART_EN);
367 }
368
369 // Fix load fw secure issue (dma_start = 1 , polling dma_done , dma_start = 0)
370 REG16_SET(&_RegOtherCtrl->CFG_OTHER_14, CFG_OHTER_14_REG_CPU_LOAD_CODE_ONLY_ONE_TIME_BY_TEE);
371
372 // Fix miu_req & miu_last
373 REG16_SET(&_RegOtherCtrl->CFG_OTHER_75, CFG_OTHER_75_REG_FIXED_MIU_REQ_FLUSH);
374
375 // Fix miu arbiter last_done_z
376 REG16_SET(&_RegTopCtrl->CFG_TOP_24, CFG_TOP_24_REG_MIU_FIXED_LAST_WD_EN_DONE_Z_ABT_ALL);
377 REG16_SET(&_RegTopCtrl->CFG_TOP_25, CFG_TOP_25_REG_CHECK_MI2RDY_ABT_ALL);
378 REG16_SET(&_RegOtherCtrl->CFG_OTHER_14, CFG_OHTER_14_REG_OR_WRITE_FIX_FOR_NEW_MIU_ARBITER_DISABLE);
379 }
380
381 // ------------ initial config ------------
382 // Sync Byte: 0x47 , 0x48 .... , 0x4e
383 // Source id : 0 , 1 , ... , 7
384 // User can use "HAL_TSP_PktConverter_SetSyncByte()" to change Sync Byte configuration
385 // , and use "HAL_TSP_PktConverter_SetSrcId()" to change Source id configuration
HAL_TSP_PktConverter_Init(void)386 void HAL_TSP_PktConverter_Init(void)
387 {
388 MS_U8 u8Path, u8Idx;
389 MS_U8 u8SyncByte, u8SrcId;
390
391 for(u8Path = 0; u8Path < TSP_TSIF_NUM; ++u8Path)
392 {
393 HAL_TSP_PktConverter_ForceSync(u8Path, TRUE); //default: FALSE
394 HAL_TSP_PktConverter_SrcIdFlt(u8Path,TRUE); //default: FALSE
395
396 u8SyncByte = 0x47;
397 u8SrcId = 0;
398
399 for(u8Idx = 0; u8Idx < TSP_MERGESTREAM_NUM; ++u8Idx,++u8SyncByte,++u8SrcId)
400 {
401 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Idx, &u8SyncByte, TRUE);
402 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Idx, &u8SrcId, TRUE);
403 }
404 }
405 }
406
HAL_TSP_Reset(MS_BOOL bEn)407 void HAL_TSP_Reset(MS_BOOL bEn)
408 {
409 FILEENG_SEQ eFileEng = E_FILEENG_TSIF0;
410
411 if(bEn)
412 {
413 // reset CMDQ
414 for(eFileEng = 0; eFileEng < TSP_TSIF_NUM; eFileEng++)
415 {
416 HAL_TSP_Filein_CmdQRst(eFileEng, TRUE);
417 }
418
419 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
420 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
421 }
422 else
423 {
424 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
425 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
426
427 for(eFileEng = 0; eFileEng < TSP_TSIF_NUM; eFileEng++)
428 {
429 HAL_TSP_Filein_CmdQRst(eFileEng, FALSE);
430 }
431 }
432 }
433
HAL_TSP_Power(MS_BOOL bEn)434 void HAL_TSP_Power(MS_BOOL bEn)
435 {
436 #ifdef CONFIG_MSTAR_CLKM
437 MS_U8 u8Idx = 0;
438 char ClkName[20] = "";
439 char Postfix[10] = "";
440 MS_S32 s32Handle;
441 #endif
442
443 if(bEn)
444 {
445 #ifdef CONFIG_MSTAR_CLKM
446
447 // Enable TSP Clk
448 s32Handle = Drv_Clkm_Get_Handle("g_clk_tsp");
449 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TSP_FAST");
450
451 // Enable STC Clk
452 for(u8Idx = 0; u8Idx < STC_ENG_NUM; u8Idx++)
453 {
454 strcpy(ClkName, "g_clk_stc");
455 sprintf(Postfix, "%d", u8Idx);
456 strcat(ClkName, Postfix);
457
458 s32Handle = Drv_Clkm_Get_Handle(ClkName);
459 Drv_Clkm_Set_Clk_Source(s32Handle, "CLK_STC0_BUF");
460 }
461
462 // Stamp
463 s32Handle = Drv_Clkm_Get_Handle("g_clk_stamp");
464 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STAMP_NORMAL");
465
466 // Parser
467 s32Handle = Drv_Clkm_Get_Handle("g_clk_parser");
468 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_PARSER_NORMAL");
469
470 // Enable TSIF => Disable TSIF
471 // FixME Enable flowset would enable TSx clk so we don't enable TSx clk
472 for(u8Idx = 0; u8Idx < TSP_TSIF_NUM; u8Idx++)
473 {
474 strcpy(ClkName, "g_clk_ts");
475 sprintf(Postfix, "%d", u8Idx);
476 strcat(ClkName, Postfix);
477
478 s32Handle = Drv_Clkm_Get_Handle(ClkName);
479 Drv_Clkm_Set_Clk_Source(s32Handle, "CLK_TS0_PAD0");
480 }
481
482 //TSO0
483 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
484 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TSOIN0_PAD0");
485
486 #else
487
488 // Enable TSP Clk
489 TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & ~REG_CLKGEN0_TSP_CLK_MASK)
490 | (REG_CLKGEN0_TSP_SRC_192MHZ << REG_CLKGEN0_TSP_SRC_SHIFT);
491
492 // Enable STC Clk
493 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) & ~REG_CLKGEN0_STC0_MASK)
494 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT));
495
496 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) & ~REG_CLKGEN0_STC1_MASK)
497 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT));
498
499 TSP_CLKGEN2_REG(REG_CLKGEN2_STC2_CLK) = (TSP_CLKGEN2_REG(REG_CLKGEN2_STC2_CLK) & ~REG_CLKGEN2_STC2_MASK)
500 | (REG_CLKGEN2_STC_SRC_SYNTH << (REG_CLKGEN2_STC_SRC_SHIFT+REG_CLKGEN2_STC2_SHIFT));
501
502 TSP_CLKGEN2_REG(REG_CLKGEN2_STC3_CLK) = (TSP_CLKGEN2_REG(REG_CLKGEN2_STC3_CLK) & ~REG_CLKGEN2_STC3_MASK)
503 | (REG_CLKGEN2_STC_SRC_SYNTH << (REG_CLKGEN2_STC_SRC_SHIFT+REG_CLKGEN2_STC3_SHIFT));
504
505 TSP_CLKGEN1_REG(REG_CLKGEN1_STC4_CLK) = (TSP_CLKGEN1_REG(REG_CLKGEN1_STC4_CLK) & ~REG_CLKGEN1_STC4_MASK)
506 | (REG_CLKGEN1_STC_SRC_SYNTH << (REG_CLKGEN1_STC_SRC_SHIFT+REG_CLKGEN1_STC4_SHIFT));
507
508 TSP_CLKGEN1_REG(REG_CLKGEN1_STC5_CLK) = (TSP_CLKGEN1_REG(REG_CLKGEN1_STC5_CLK) & ~REG_CLKGEN1_STC5_MASK)
509 | (REG_CLKGEN1_STC_SRC_SYNTH << (REG_CLKGEN1_STC_SRC_SHIFT+REG_CLKGEN1_STC5_SHIFT));
510
511 TSP_CLKGEN1_REG(REG_CLKGEN1_STC6_CLK) = (TSP_CLKGEN1_REG(REG_CLKGEN1_STC6_CLK) & ~REG_CLKGEN1_STC6_MASK)
512 | (REG_CLKGEN1_STC_SRC_SYNTH << (REG_CLKGEN1_STC_SRC_SHIFT+REG_CLKGEN1_STC6_SHIFT));
513
514 TSP_CLKGEN1_REG(REG_CLKGEN1_STC7_CLK) = (TSP_CLKGEN1_REG(REG_CLKGEN1_STC7_CLK) & ~REG_CLKGEN1_STC7_MASK)
515 | (REG_CLKGEN1_STC_SRC_SYNTH << (REG_CLKGEN1_STC_SRC_SHIFT+REG_CLKGEN1_STC7_SHIFT));
516
517 // Stamp
518 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) & ~REG_CLKGEN0_STAMP_MASK);
519
520 // Parser
521 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) & ~REG_CLKGEN0_PARSER_MASK);
522
523 // Enable TSIF => Disable TSIF
524 // FixME Enable flowset would enable TSx clk so we don't enable TSx clk
525 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS0_SHIFT));
526 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS1_SHIFT));
527 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS2_SHIFT));
528 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS3_SHIFT));
529 TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS4_SHIFT));
530 TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS5_SHIFT));
531 TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS6_SHIFT));
532
533 //TSO0
534 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) & ~REG_CLKGEN0_TS_MASK);
535
536 #endif
537
538 // TSP Boot clk sel
539 TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) = (TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) & ~REG_TOP_TSP_BOOT_CLK_SEL_MASK) | REG_TOP_TSP_BOOT_CLK_SEL_TSP;
540
541 // TSP SRAM sel
542 TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) = TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) | REG_MMFI_TSP_SEL_SRAM_EN;
543
544 REG16_SET(&_RegOtherCtrl->CFG_OTHER_16, CFG_OHTER_16_REG_PREVENT_SRAM_COLLISION);
545
546 // Disable MCM
547 REG16_SET(&_RegOtherCtrl->CFG_OTHER_13, CFG_OHTER_13_REG_TSP2MI_REQ_MCM_DISABLE)
548 }
549 else
550 {
551 // Enable MCM
552 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_13, CFG_OHTER_13_REG_TSP2MI_REQ_MCM_DISABLE);
553
554 #ifdef CONFIG_MSTAR_CLKM
555
556 MS_S32 s32Handle;
557
558 // Disable TSP Clk
559 // [2016.03.10] Disable TSP clk for power problem. If AESDMA share clk with TSP. Need to do tsp init before using AESDMA.
560 s32Handle = Drv_Clkm_Get_Handle("g_clk_tsp");
561 Drv_Clkm_Clk_Gate_Disable(s32Handle);
562
563 // Disable STC Clk
564 for(u8Idx = 0; u8Idx < STC_ENG_NUM; u8Idx++)
565 {
566 strcpy(ClkName, "g_clk_stc");
567 sprintf(Postfix, "%d", u8Idx);
568 strcat(ClkName, Postfix);
569
570 s32Handle = Drv_Clkm_Get_Handle(ClkName);
571 Drv_Clkm_Clk_Gate_Disable(s32Handle);
572 }
573
574 // Stamp
575 s32Handle = Drv_Clkm_Get_Handle("g_clk_stamp");
576 Drv_Clkm_Clk_Gate_Disable(s32Handle);
577
578 // Parser
579 s32Handle = Drv_Clkm_Get_Handle("g_clk_parser");
580 Drv_Clkm_Clk_Gate_Disable(s32Handle);
581
582 // Disable TSIF
583 for(u8Idx = 0; u8Idx < TSP_TSIF_NUM; u8Idx++)
584 {
585 strcpy(ClkName, "g_clk_ts");
586 sprintf(Postfix, "%d", u8Idx);
587 strcat(ClkName, Postfix);
588
589 s32Handle = Drv_Clkm_Get_Handle(ClkName);
590 Drv_Clkm_Clk_Gate_Disable(s32Handle);
591 }
592
593 //TSO0
594 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
595 Drv_Clkm_Clk_Gate_Disable(s32Handle);
596
597 #else
598 // Disable TSP Clk
599 // [2016.03.10] Disable TSP clk for power problem. If AESDMA share clk with TSP. Need to do tsp init before using AESDMA.
600 TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK),(REG_CLKGEN0_TSP_DISABLE << REG_CLKGEN0_TSP_SHIFT));
601
602 // Disable STC Clk
603 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC0_SHIFT));
604 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC1_SHIFT));
605 TSP_CLKGEN2_REG(REG_CLKGEN2_STC2_CLK) = _SET_(TSP_CLKGEN2_REG(REG_CLKGEN2_STC2_CLK),(REG_CLKGEN2_STC_DISABLE << REG_CLKGEN2_STC2_SHIFT));
606 TSP_CLKGEN2_REG(REG_CLKGEN2_STC3_CLK) = _SET_(TSP_CLKGEN2_REG(REG_CLKGEN2_STC3_CLK),(REG_CLKGEN2_STC_DISABLE << REG_CLKGEN2_STC3_SHIFT));
607 TSP_CLKGEN1_REG(REG_CLKGEN1_STC4_CLK) = _SET_(TSP_CLKGEN1_REG(REG_CLKGEN1_STC4_CLK),(REG_CLKGEN1_STC_DISABLE << REG_CLKGEN1_STC4_SHIFT));
608 TSP_CLKGEN1_REG(REG_CLKGEN1_STC5_CLK) = _SET_(TSP_CLKGEN1_REG(REG_CLKGEN1_STC5_CLK),(REG_CLKGEN1_STC_DISABLE << REG_CLKGEN1_STC5_SHIFT));
609 TSP_CLKGEN1_REG(REG_CLKGEN1_STC6_CLK) = _SET_(TSP_CLKGEN1_REG(REG_CLKGEN1_STC6_CLK),(REG_CLKGEN1_STC_DISABLE << REG_CLKGEN1_STC6_SHIFT));
610 TSP_CLKGEN1_REG(REG_CLKGEN1_STC7_CLK) = _SET_(TSP_CLKGEN1_REG(REG_CLKGEN1_STC7_CLK),(REG_CLKGEN1_STC_DISABLE << REG_CLKGEN1_STC7_SHIFT));
611
612 // Stamp
613 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK),(REG_CLKGEN0_STAMP_DISABLE << REG_CLKGEN0_STAMP_SHIFT));
614
615 // Parser
616 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK),(REG_CLKGEN0_PARSER_DISABLE << REG_CLKGEN0_PARSER_SHIFT));
617
618 // Disable TSIF clk
619 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS0_SHIFT));
620 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS1_SHIFT));
621 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS2_SHIFT));
622 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS3_SHIFT));
623 TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS4_SHIFT));
624 TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS5_SHIFT));
625 TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS6_SHIFT));
626
627 //TSO0
628 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TSO0_SHIFT));
629
630 #endif
631
632 }
633 }
634
HAL_TSP_CPU(MS_BOOL bEn)635 void HAL_TSP_CPU(MS_BOOL bEn)
636 {
637 if (bEn)
638 {
639 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
640 }
641 else
642 {
643 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
644 }
645 }
646
HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr,MS_U32 u32FwSize)647 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize)
648 {
649
650 #define _TSP_QMEM_I_MASK 0xffff8000 //code: 0x2000, data: 0x1000, total: 0x3000
651 #define _TSP_QMEM_I_ADDR_HIT 0x00000000
652 #define _TSP_QMEM_I_ADDR_MISS 0xffffffff
653 #define _TSP_QMEM_D_MASK 0xffff8000
654 #define _TSP_QMEM_D_ADDR_HIT 0x00000000
655 #define _TSP_QMEM_D_ADDR_MISS 0xffffffff
656 #define _TSP_QMEM_SIZE 0x2000 // 32K bytes, 32bit aligment //0x8000 this is 4 byte address
657
658 REG32_W(&_RegCtrl->Cpu_Base, 0); // 16 bytes address unit
659
660 MS_U32 u32DnldCtrl = 0;
661 MS_U32 u32DnldCtrl1 = 0;
662
663 // Check MIU select
664 MS_U8 u8MiuSel = 0;
665 MS_PHY phyMiuOffsetFWBuf = 0;
666
667 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFWBuf, u32FwPhyAddr);
668 REG16_MSK_W(&_RegTopCtrl->CFG_TOP_08, CFG_TOP_08_REG_MIU_SEL_FILEIN_MASK, u8MiuSel); //Filein #0
669
670 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT;
671 u32DnldCtrl1 = u32DnldCtrl >> 16;
672
673 REG16_W(&_RegCtrl->Dnld_Ctrl_Addr, (MS_U16)(u32DnldCtrl & TSP_DNLD_ADDR_MASK)); // oneway register
674 REG16_MSK_W(&_RegCtrl->Dnld_AddrH, TSP_DMA_RADDR_MSB_MASK, (MS_U16)u32DnldCtrl1);
675 REG16_W(&_RegCtrl->Dnld_Ctrl_Size, _TSP_QMEM_SIZE);
676 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
677 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START);
678
679 //@TODO temprarily comment because of Secure Protect
680 #if 1
681 while (!(REG16_R(&_RegCtrl->TSP_Ctrl) & TSP_CTRL_DNLD_DONE))
682 {
683 }
684 #endif
685
686 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
687
688 REG32_W(&_RegCtrl->Qmem_Imask, _TSP_QMEM_I_MASK);
689 REG32_W(&_RegCtrl->Qmem_Ibase, _TSP_QMEM_I_ADDR_HIT);
690 REG32_W(&_RegCtrl->Qmem_Dmask, _TSP_QMEM_D_MASK);
691 REG32_W(&_RegCtrl->Qmem_Dbase, _TSP_QMEM_D_ADDR_HIT);
692
693 #undef _TSP_QMEM_I_MASK
694 #undef _TSP_QMEM_I_ADDR_HIT
695 #undef _TSP_QMEM_I_ADDR_MISS
696 #undef _TSP_QMEM_D_MASK
697 #undef _TSP_QMEM_D_ADDR_HIT
698 #undef _TSP_QMEM_D_ADDR_MISS
699 #undef _TSP_QMEM_SIZE
700
701 return TRUE;
702 }
703
HAL_TSP_RestoreFltState(void)704 void HAL_TSP_RestoreFltState(void)
705 {
706 MS_U32 u32Size;
707 TSP32 * pRegEnd;
708 TSP32 * pReg;
709 int i, j;
710
711 for (i = 0; i < TSP_PIDFLT_NUM; i++)
712 {
713 TSP32_IdrW(&(_REGPid0->Flt[i]), _u32PidFltReg[i]);
714 TSP32_IdrW(&(_REGPid1->Flt[i]), _u32PidDstReg[i]);
715 TSP32_IdrW(&(_REGPid2->Flt[i]), _u32PidDst2Reg[i]);
716 }
717
718 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x54))/sizeof(TSP32);
719
720 for (i = 0; i < TSP_SECFLT_NUM; i++)
721 {
722 pReg = (TSP32*)&(_REGSec->Flt[i]);
723 pRegEnd = pReg + u32Size;
724 j = 0;
725 for ( ; pReg < pRegEnd; pReg++)
726 {
727 TSP32_IdrW(pReg, _u32SecReg[i*u32Size+j]);
728 j++;
729 }
730 }
731
732 }
733
HAL_TSP_SetTSIF(MS_U16 u16TSIF,TSP_TSIF_CFG u16Cfg,MS_BOOL bFileIn)734 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn)
735 {
736 if(bFileIn)
737 {
738 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, TRUE); // this returns true only we don't check the return value
739 HAL_TSP_TSIF_LiveEn(u16TSIF, FALSE); // this returns true only we don't check the return value
740 }
741 else
742 {
743 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, FALSE);
744 HAL_TSP_TSIF_LiveEn(u16TSIF, TRUE);
745 }
746
747 if(bFileIn != TRUE)
748 {
749 HAL_TSP_TSIF_BitSwap(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_BITSWAP)?TRUE:FALSE));
750 HAL_TSP_TSIF_ExtSync(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_EXTSYNC)?TRUE:FALSE));
751 HAL_TSP_TSIF_Parl (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_PARA )?TRUE:FALSE));
752 HAL_TSP_TSIF_3Wire (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_3WIRE )?TRUE:FALSE));
753 }
754
755 return TRUE;
756 }
757
HAL_TSP_TSIF_LiveEn(MS_U32 tsIf,MS_BOOL bEnable)758 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable)
759 {
760 if(tsIf >= TSP_TSIF_NUM)
761 {
762 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,tsIf));
763 return FALSE;
764 }
765
766 if(bEnable)
767 {
768 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_TS_IF_EN);
769 }
770 else
771 {
772 REG16_CLR(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_TS_IF_EN);
773 }
774
775 return TRUE;
776 }
777
HAL_TSP_TSIF_SelPad(MS_U32 tsIf,TSP_TS_PAD eTSPad)778 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad)
779 {
780 if(tsIf >= TSP_TSIF_NUM)
781 {
782 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,tsIf));
783 return FALSE;
784 }
785
786 MS_U32 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
787 MS_U32 pad_src = CFG_TSP_SRC_MUX_PAD_TS0;
788 #ifdef CONFIG_MSTAR_CLKM
789 MS_S32 handle;
790 MS_U8 u8NameIdx = 0;
791 char* u8ClkSrcNames[] =
792 {
793 "CLK_TS0_PAD0",
794 "CLK_TS0_PAD1",
795 "CLK_TS0_PAD2",
796 "CLK_TS0_PAD3",
797 "CLK_TS0_PAD4",
798 "CLK_TS0_PAD5",
799 "CLK_TS0_PAD6",
800 "CLK_TS0_PADTSO",
801 "CLK_TS0_PADTSIO"
802 /*
803 "CLK_TS0_PADINTER0",
804 "CLK_TS0_PADINTER1"
805 */
806 };
807 #endif
808
809 //@NOTE
810 //EX3~6 are serial mode and ts2_padmax_mode must be 2 or 3.
811
812 switch (eTSPad)
813 {
814 default:
815 case E_TSP_TS_PAD_EXT0:
816 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
817 pad_src = CFG_TSP_SRC_MUX_PAD_TS0;
818 break;
819 case E_TSP_TS_PAD_EXT1:
820 clk_src = REG_CLKGEN0_TS_SRC_EXT1;
821 pad_src = CFG_TSP_SRC_MUX_PAD_TS1;
822 break;
823 case E_TSP_TS_PAD_EXT2:
824 clk_src = REG_CLKGEN0_TS_SRC_EXT2;
825 pad_src = CFG_TSP_SRC_MUX_PAD_TS2;
826 break;
827 case E_TSP_TS_PAD_EXT3:
828 clk_src = REG_CLKGEN0_TS_SRC_EXT3;
829 pad_src = CFG_TSP_SRC_MUX_PAD_TS3;
830 break;
831 case E_TSP_TS_PAD_EXT4:
832 clk_src = REG_CLKGEN0_TS_SRC_EXT4;
833 pad_src = CFG_TSP_SRC_MUX_PAD_TS4;
834 break;
835 case E_TSP_TS_PAD_EXT5:
836 clk_src = REG_CLKGEN0_TS_SRC_EXT5;
837 pad_src = CFG_TSP_SRC_MUX_PAD_TS5;
838 break;
839 case E_TSP_TS_PAD_EXT6:
840 clk_src = REG_CLKGEN0_TS_SRC_EXT6;
841 pad_src = CFG_TSP_SRC_MUX_PAD_TS6;
842 break;
843 case E_TSP_TS_PAD_EXT7:
844 clk_src = REG_CLKGEN0_TS_SRC_EXT7;
845 pad_src = CFG_TSP_SRC_MUX_PAD_TS7;
846 break;
847 case E_TSP_TS_PAD_TSOUT0:
848 clk_src = REG_CLKGEN0_TS_SRC_TSO0;
849 pad_src = CFG_TSP_SRC_MUX_PAD_TSO0;
850 break;
851 case E_TSP_TS_PAD_TSOUT1:
852 clk_src = REG_CLKGEN0_TS_SRC_TSO1;
853 pad_src = CFG_TSP_SRC_MUX_PAD_TSO1;
854 break;
855 case E_TSP_TS_PAD_TSIOOUT0:
856 clk_src = REG_CLKGEN0_TS_SRC_TSIO0;
857 pad_src = CFG_TSP_SRC_MUX_PAD_TSIO;
858 break;
859 }
860
861 if(tsIf & 0x1) // Odd
862 {
863 REG16_MSK_W(&_RegTspSrcCtrl->CFG_TSP_SRC_00_03[(tsIf >> 1)], CFG_TSP_SRC_MUX_ODD_MASK, (pad_src << CFG_TSP_SRC_MUX_ODD_SHIFT));
864 }
865 else // Even
866 {
867 REG16_MSK_W(&_RegTspSrcCtrl->CFG_TSP_SRC_00_03[(tsIf >> 1)], CFG_TSP_SRC_MUX_EVEN_MASK, (pad_src << CFG_TSP_SRC_MUX_EVEN_SHIFT));
868 }
869
870 #ifdef CONFIG_MSTAR_CLKM
871 char TspClkName[20] = "g_clk_ts";
872 char postfix[10] = "";
873
874 sprintf(postfix, "%d", tsIf);
875 strcat(TspClkName, postfix);
876
877 handle = Drv_Clkm_Get_Handle(TspClkName);
878 u8NameIdx = clk_src - REG_CLKGEN0_TS_SRC_EXT0;
879 Drv_Clkm_Set_Clk_Source(handle, u8ClkSrcNames[u8NameIdx]);
880 #else
881 switch (tsIf)
882 {
883 case TSP_TSIF0:
884 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS0_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
885 break;
886 case TSP_TSIF1:
887 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS1_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
888 break;
889 case TSP_TSIF2:
890 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS2_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
891 break;
892 case TSP_TSIF3:
893 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS3_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
894 break;
895 case TSP_TSIF4:
896 TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS4_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS4_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
897 break;
898 case TSP_TSIF5:
899 TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS5_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS5_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
900 break;
901 case TSP_TSIF6:
902 TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS6_SHIFT)) | (clk_src<<(REG_CLKGEN0_TS6_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
903 break;
904 default:
905 return FALSE;
906 }
907 #endif
908
909 return TRUE;
910 }
911
HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)912 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)
913 {
914 //@NOTE: K7U don't have to implement (this function is used for TSO 1.0)
915 }
916
HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng,TSP_TS_PAD eTSPad)917 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad)
918 {
919 //@NOTE: K7U don't have to implement (this function is used for TSO 1.0)
920 return TRUE;
921 }
922
923
HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf,MS_BOOL bClkInv)924 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv)
925 {
926 if (bClkInv)
927 {
928 switch (tsIf)
929 {
930 case 0:
931 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
932 break;
933 case 1:
934 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
935 break;
936 case 2:
937 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
938 break;
939 case 3:
940 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT));
941 break;
942 case 4:
943 TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS4_SHIFT));
944 break;
945 case 5:
946 TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS5_SHIFT));
947 break;
948 case 6:
949 TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS6_SHIFT));
950 break;
951 default:
952 return FALSE;
953 }
954 }
955 else
956 {
957 switch (tsIf)
958 {
959 case 0:
960 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
961 break;
962 case 1:
963 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
964 break;
965 case 2:
966 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
967 break;
968 case 3:
969 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT));
970 break;
971 case 4:
972 TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS4_SHIFT));
973 break;
974 case 5:
975 TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS5_SHIFT));
976 break;
977 case 6:
978 TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS6_SHIFT));
979 break;
980 default:
981 return FALSE;
982 }
983 }
984 return TRUE;
985 }
986
HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf,MS_BOOL bClkDis)987 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis)
988 {
989 if(tsIf >= TSP_TSIF_NUM)
990 {
991 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,tsIf));
992 return FALSE;
993 }
994
995 #ifdef CONFIG_MSTAR_CLKM
996 MS_S32 s32Handle;
997 char TspClkName[20] = "g_clk_ts";
998 char postfix[10] = "";
999
1000 sprintf(postfix, "%d", tsIf);
1001 strcat(TspClkName, postfix);
1002 #endif
1003
1004 if (bClkDis)
1005 {
1006 #ifdef CONFIG_MSTAR_CLKM
1007 s32Handle = Drv_Clkm_Get_Handle(TspClkName);
1008 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1009 #else
1010 switch (tsIf)
1011 {
1012 case 0:
1013 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
1014 break;
1015 case 1:
1016 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
1017 break;
1018 case 2:
1019 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
1020 break;
1021 case 3:
1022 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT));
1023 break;
1024 case 4:
1025 TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS4_SHIFT));
1026 break;
1027 case 5:
1028 TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS5_SHIFT));
1029 break;
1030 case 6:
1031 TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS6_SHIFT));
1032 break;
1033 default:
1034 return FALSE;
1035 }
1036 #endif
1037 }
1038 else
1039 {
1040 #ifdef CONFIG_MSTAR_CLKM
1041 MS_U16 u16ClkSrc;
1042 MS_U8 u8NameIdx = 0;
1043 char* u8ClkSrcNames[] =
1044 {
1045 "CLK_TS0_PAD0",
1046 "CLK_TS0_PAD1",
1047 "CLK_TS0_PAD2",
1048 "CLK_TS0_PAD3",
1049 "CLK_TS0_PAD4",
1050 "CLK_TS0_PAD5",
1051 "CLK_TS0_PAD6",
1052 "CLK_TS0_PADTSO",
1053 "CLK_TS0_PADTSIO"
1054 };
1055
1056 switch (tsIf)
1057 {
1058 case 0:
1059 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS0_SHIFT)) >> (REG_CLKGEN0_TS0_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1060 break;
1061 case 1:
1062 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT)) >> (REG_CLKGEN0_TS1_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1063 break;
1064 case 2:
1065 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT)) >> (REG_CLKGEN0_TS2_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1066 break;
1067 case 3:
1068 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) >> (REG_CLKGEN0_TS3_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1069 break;
1070 case 4:
1071 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS4_SHIFT)) >> (REG_CLKGEN0_TS4_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1072 break;
1073 case 5:
1074 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS5_SHIFT)) >> (REG_CLKGEN0_TS5_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1075 break;
1076 case 6:
1077 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS6_SHIFT)) >> (REG_CLKGEN0_TS6_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1078 break;
1079 default:
1080 return FALSE;
1081 }
1082
1083 if(u16ClkSrc > REG_CLKGEN0_TS_SRC_TSIO0)
1084 {
1085 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1086 return FALSE;
1087 }
1088
1089 s32Handle = Drv_Clkm_Get_Handle(TspClkName);
1090 u8NameIdx = u16ClkSrc - REG_CLKGEN0_TS_SRC_EXT0;
1091 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcNames[u8NameIdx]);
1092 #else
1093 switch (tsIf)
1094 {
1095 case 0:
1096 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
1097 break;
1098 case 1:
1099 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
1100 break;
1101 case 2:
1102 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
1103 break;
1104 case 3:
1105 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT));
1106 break;
1107 case 4:
1108 TSP_CLKGEN0_REG(REG_CLKGEN0_TS4_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS4_SHIFT));
1109 break;
1110 case 5:
1111 TSP_CLKGEN0_REG(REG_CLKGEN0_TS5_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS5_SHIFT));
1112 break;
1113 case 6:
1114 TSP_CLKGEN0_REG(REG_CLKGEN0_TS6_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS6_SHIFT));
1115 break;
1116 default:
1117 return FALSE;
1118 }
1119 #endif
1120 }
1121
1122 return TRUE;
1123 }
1124
HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1125 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1126 {
1127 if(eFileEng >= TSP_TSIF_NUM)
1128 {
1129 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1130 return FALSE;
1131 }
1132
1133 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1134 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1135
1136 if(bEnable)
1137 {
1138 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_TSP_FILE_SEGMENT);
1139 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TS_DATA_PORT_SEL);
1140 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_TSP_FILE_IN);
1141 }
1142 else
1143 {
1144 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_TSP_FILE_SEGMENT);
1145 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TS_DATA_PORT_SEL);
1146 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_TSP_FILE_IN);
1147 }
1148
1149 return TRUE;
1150 }
1151
HAL_TSP_TSIF_BitSwap(MS_U32 tsIf,MS_BOOL bEnable)1152 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable)
1153 {
1154 if(tsIf >= TSP_TSIF_NUM)
1155 {
1156 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,tsIf));
1157 return;
1158 }
1159
1160 if(bEnable)
1161 {
1162 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_TS_DATA_SWAP);
1163 }
1164 else
1165 {
1166 REG16_CLR(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_TS_DATA_SWAP);
1167 }
1168 }
1169
HAL_TSP_TSIF_ExtSync(MS_U32 tsIf,MS_BOOL bEnable)1170 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable)
1171 {
1172 if(tsIf >= TSP_TSIF_NUM)
1173 {
1174 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,tsIf));
1175 return;
1176 }
1177
1178 if(bEnable)
1179 {
1180 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_EXT_SYNC_SEL);
1181 }
1182 else
1183 {
1184 REG16_CLR(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_EXT_SYNC_SEL);
1185 }
1186 }
1187
HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng,MS_BOOL bBypass)1188 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bBypass)
1189 {
1190 if(eFileEng >= TSP_TSIF_NUM)
1191 {
1192 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1193 return;
1194 }
1195
1196 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1197 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1198
1199 if(bBypass)
1200 {
1201 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_PS_MODE_BLOCK);
1202 }
1203 else
1204 {
1205 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_PS_MODE_BLOCK);
1206 }
1207 }
1208
HAL_TSP_TSIF_Parl(MS_U32 tsIf,MS_BOOL bEnable)1209 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable)
1210 {
1211 if(tsIf >= TSP_TSIF_NUM)
1212 {
1213 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,tsIf));
1214 return;
1215 }
1216
1217 if(bEnable)
1218 {
1219 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_P_SEL);
1220 }
1221 else
1222 {
1223 REG16_CLR(&_RegPathCtrl[tsIf].CFG_PATH_00, CFG_PATH_00_REG_P_SEL);
1224 }
1225 }
1226
HAL_TSP_PAD_3Wire(MS_U32 u32Pad,MS_BOOL bEnable)1227 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable)
1228 {
1229 //@NOTE: After Kano , do NOT need to set
1230 }
1231
HAL_TSP_TSIF_3Wire(MS_U32 tsIf,MS_BOOL bEnable)1232 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable)
1233 {
1234 if(tsIf >= TSP_TSIF_NUM)
1235 {
1236 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,tsIf));
1237 return;
1238 }
1239
1240 if(bEnable)
1241 {
1242 REG16_SET(&_RegOtherCtrl->CFG_OTHER_13, (CFG_OTHER_13_REG_3WIRE_SERIAL_MODE_EN << tsIf));
1243 }
1244 else
1245 {
1246 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_13, (CFG_OTHER_13_REG_3WIRE_SERIAL_MODE_EN << tsIf));
1247 }
1248 }
1249
HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng,MS_U32 u32PktSize)1250 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize)
1251 {
1252 if(eFileEng >= TSP_TSIF_NUM)
1253 {
1254 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1255 return;
1256 }
1257
1258 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1259 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1260 MS_U16 u16PktLen = u32PktSize, u16value = 0;
1261
1262
1263 if(u32PktSize == 130)
1264 {
1265 u16PktLen = 188;
1266 }
1267 else if(u32PktSize == 134)
1268 {
1269 u16PktLen = 192;
1270 }
1271
1272 if(u32PktSize == 130 || u32PktSize == 134) //RVU
1273 {
1274 u16value = CFG_FILE_0E_REG_RVU_EN | CFG_FILE_0E_REG_RVU_PSI_EN;
1275
1276 if(u32PktSize == 134)
1277 {
1278 u16value |= CFG_FILE_0E_REG_RVU_TIMESTAMP_EN;
1279 }
1280
1281 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0E, u16value);
1282 }
1283 else
1284 {
1285 u16value = CFG_FILE_0E_REG_RVU_EN | CFG_FILE_0E_REG_RVU_PSI_EN | CFG_FILE_0E_REG_RVU_TIMESTAMP_EN;
1286 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_0E, u16value);
1287 }
1288
1289 // file-in init trust count value
1290 REG16_MSK_W(&RegFileCtrl[u8FileEng].CFG_FILE_0A, CFG_FILE_0A_REG_INIT_TRUST_SYNC_CNT_VALUE_MASK, u16PktLen << CFG_FILE_0A_REG_INIT_TRUST_SYNC_CNT_VALUE_SHIFT);
1291 REG16_MSK_W(&RegFileCtrl[u8FileEng].CFG_FILE_08, CFG_FILE_08_REG_CHK_PKT_SIZE_MASK, (u16PktLen-1) << CFG_FILE_08_REG_CHK_PKT_SIZE_SHIFT);
1292 }
1293
HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng,MS_U32 addr)1294 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr)
1295 {
1296 if(eFileEng >= TSP_TSIF_NUM)
1297 {
1298 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1299 return;
1300 }
1301
1302 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1303 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1304
1305 // Check MIU select
1306 MS_U8 u8MiuSel;
1307 MS_PHY phyMiuOffsetFileinAddr;
1308 MS_U16 u8Shift = eFileEng * TSP_MIU_SEL_BITS_LEN;
1309
1310 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinAddr, addr);
1311 REG16_MSK_W(&_RegTopCtrl->CFG_TOP_08, (CFG_TOP_08_REG_MIU_SEL_FILEIN_MASK << u8Shift), (u8MiuSel << (CFG_TOP_08_REG_MIU_SEL_FILEIN_SHIFT + u8Shift)));
1312 REG32_W(&RegFileCtrl[u8FileEng].CFG_FILE_02_03, phyMiuOffsetFileinAddr);
1313 }
1314
HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng,MS_U32 size)1315 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size)
1316 {
1317 if(eFileEng >= TSP_TSIF_NUM)
1318 {
1319 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1320 return;
1321 }
1322
1323 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1324 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1325
1326 REG32_W(&RegFileCtrl[u8FileEng].CFG_FILE_04_05, size);
1327 }
1328
HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)1329 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)
1330 {
1331 if(eFileEng >= TSP_TSIF_NUM)
1332 {
1333 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1334 return;
1335 }
1336
1337 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1338 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1339
1340 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_06, CFG_FILE_06_REG_FILEIN_RSTART);
1341 }
1342
HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)1343 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)
1344 {
1345 if(eFileEng >= TSP_TSIF_NUM)
1346 {
1347 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1348 return FALSE;
1349 }
1350
1351 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1352 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1353
1354 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TSIF_PAUSE);
1355 return TRUE;
1356 }
1357
HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)1358 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)
1359 {
1360 if(eFileEng >= TSP_TSIF_NUM)
1361 {
1362 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1363 return FALSE;
1364 }
1365
1366 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1367 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1368
1369 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TSIF_PAUSE);
1370 return TRUE;
1371 }
1372
1373 #if FPGA_TEST
1374
HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng)1375 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng)
1376 {
1377 return !HAL_TSP_Filein_Status(eFileEng);
1378 }
1379
HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)1380 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)
1381 {
1382 if(eFileEng >= TSP_TSIF_NUM)
1383 {
1384 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1385 return;
1386 }
1387
1388 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1389 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1390
1391 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_06, (CFG_FILE_06_REG_FILEIN_RSTART | CFG_FILE_06_REG_FILEIN_INIT_TRUST));
1392 }
1393
HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1394 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1395 {
1396 if(eFileEng >= TSP_TSIF_NUM)
1397 {
1398 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1399 return;
1400 }
1401
1402 if(bEnable)
1403 {
1404 REG16_SET(&_RegOtherCtrl->CFG_OTHER_19, (CFG_OTHER_19_REG_FILEIN0_DMAR_PROTECT_EN << eFileEng));
1405 }
1406 else
1407 {
1408 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_19, (CFG_OTHER_19_REG_FILEIN0_DMAR_PROTECT_EN << eFileEng));
1409 }
1410 }
1411
HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)1412 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
1413 {
1414 if(eFileEng >= TSP_TSIF_NUM)
1415 {
1416 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1417 return;
1418 }
1419
1420 MS_U8 u8MiuSel;
1421 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
1422
1423 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
1424 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
1425
1426 if(u8MiuSel < E_CHIP_MIU_NUM)
1427 {
1428 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK);
1429 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK);
1430
1431 REG32_W(&_RegTopCtrl->CFG_TOP_30_4B[eFileEng].L_BND, u32LBnd);
1432 REG32_W(&_RegTopCtrl->CFG_TOP_30_4B[eFileEng].U_BND, u32UBnd);
1433 }
1434 }
1435
1436 #endif
1437
HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng,MS_BOOL bEn)1438 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn)
1439 {
1440 if(eFileEng >= TSP_TSIF_NUM)
1441 {
1442 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1443 return;
1444 }
1445
1446 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1447 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1448
1449 if(bEn)
1450 {
1451 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TSP_FILEIN_ABORT);
1452 }
1453 else
1454 {
1455 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TSP_FILEIN_ABORT);
1456 }
1457 }
1458
HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1459 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1460 {
1461 if(eFileEng >= TSP_TSIF_NUM)
1462 {
1463 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1464 return;
1465 }
1466
1467 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1468 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1469
1470 if(bEnable)
1471 {
1472 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_RST_CMDQ_FILEIN);
1473 }
1474 else
1475 {
1476 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_RST_CMDQ_FILEIN);
1477 }
1478 }
1479
HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)1480 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)
1481 {
1482 if(eFileEng >= TSP_TSIF_NUM)
1483 {
1484 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1485 return 0;
1486 }
1487
1488 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1489 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1490
1491 return 16 - ((REG16_R(&RegFileCtrl[u8FileEng].CFG_FILE_07) & CFG_FILE_07_CMD_WR_CNT_TSIF1_MASK) >> CFG_FILE_07_CMD_WR_CNT_TSIF1_SHIFT);
1492 }
1493
HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)1494 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)
1495 {
1496 if(eFileEng >= TSP_TSIF_NUM)
1497 {
1498 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1499 return 0;
1500 }
1501
1502 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1503 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1504
1505 return ((REG16_R(&RegFileCtrl[u8FileEng].CFG_FILE_07) & CFG_FILE_07_CMD_WR_CNT_TSIF1_MASK) >> CFG_FILE_07_CMD_WR_CNT_TSIF1_SHIFT);
1506 }
1507
HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)1508 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)
1509 {
1510 if(eFileEng >= TSP_TSIF_NUM)
1511 {
1512 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1513 return 0;
1514 }
1515
1516 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1517 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1518
1519 return ((REG16_R(&RegFileCtrl[u8FileEng].CFG_FILE_07) & CFG_FILE_07_CMD_WR_LEVEL_TSIF1_MASK) >> CFG_FILE_07_CMD_WR_LEVEL_TSIF1_SHIFT);
1520 }
1521
HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng,MS_U32 delay,MS_BOOL bEnable)1522 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable)
1523 {
1524 if(eFileEng >= TSP_TSIF_NUM)
1525 {
1526 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1527 return;
1528 }
1529
1530 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1531 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1532
1533 if(bEnable)
1534 {
1535 REG16_W(&RegFileCtrl[u8FileEng].CFG_FILE_09, delay);
1536 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TIMER_EN);
1537 }
1538 else
1539 {
1540 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_TIMER_EN);
1541 REG16_W(&RegFileCtrl[u8FileEng].CFG_FILE_09, 0x0000);
1542 }
1543 }
1544
HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)1545 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)
1546 {
1547 if(eFileEng >= TSP_TSIF_NUM)
1548 {
1549 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1550 return 0;
1551 }
1552
1553 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1554 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1555
1556 return !(REG16_R(&RegFileCtrl[u8FileEng].CFG_FILE_06) & CFG_FILE_06_REG_FILEIN_DONE);
1557 }
1558
HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)1559 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)
1560 {
1561 TSP_HAL_FileState state = E_TSP_HAL_FILE_STATE_INVALID;
1562 MS_U32 u32Status = HAL_TSP_Filein_Status(eFileEng);
1563
1564 if(eFileEng >= TSP_TSIF_NUM)
1565 {
1566 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1567 return E_TSP_HAL_FILE_STATE_INVALID;
1568 }
1569
1570 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1571 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1572
1573 if(REG16_R(&RegFileCtrl[u8FileEng].CFG_FILE_01) & CFG_FILE_01_REG_TSIF_PAUSE)
1574 {
1575 state = E_TSP_HAL_FILE_STATE_PAUSE;
1576 }
1577 else if(u32Status)
1578 {
1579 state = E_TSP_HAL_FILE_STATE_BUSY;
1580 }
1581 else
1582 {
1583 state = E_TSP_HAL_FILE_STATE_IDLE;
1584 }
1585
1586 return state;
1587 }
1588
HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet)1589 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng, MS_BOOL bSet)
1590 {
1591 if(eFileEng >= TSP_TSIF_NUM)
1592 {
1593 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1594 return;
1595 }
1596
1597 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1598 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1599
1600 if(bSet)
1601 {
1602 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_PKT192_EN);
1603 }
1604 else
1605 {
1606 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_PKT192_EN);
1607 }
1608 }
1609
HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng,MS_BOOL bEn)1610 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn)
1611 {
1612 if(eFileEng >= TSP_TSIF_NUM)
1613 {
1614 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1615 return;
1616 }
1617
1618 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1619 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1620
1621 if(bEn)
1622 {
1623 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_PKT192_BLK_DISABLE);
1624 }
1625 else
1626 {
1627 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_PKT192_BLK_DISABLE);
1628 }
1629 }
1630
HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng,MS_U32 u32Stamp)1631 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp)
1632 {
1633 if(eFileEng >= TSP_TSIF_NUM)
1634 {
1635 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1636 return;
1637 }
1638
1639 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1640 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1641
1642 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_LPCR2_WLD);
1643 REG32_W(&RegFileCtrl[u8FileEng].CFG_FILE_10_11, u32Stamp);
1644 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_LPCR2_WLD);
1645
1646 // Fix pass_pkt_timestamp will hang issue by TSP8,0x60[3] : reg_init_timestamp_restart_en
1647 // _HAL_TSP_FILEIN_ResetPktTimeStamp(eFileEng, 0);
1648 }
1649
HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng,TSP_HAL_TimeStamp_Clk eTimeStampClk)1650 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk)
1651 {
1652 if(eFileEng >= TSP_TSIF_NUM)
1653 {
1654 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1655 return;
1656 }
1657
1658 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1659 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1660
1661 if(eTimeStampClk == E_TSP_HAL_TIMESTAMP_CLK_27M)
1662 {
1663 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_LPCR_FREG_27M_90K);
1664 }
1665 else
1666 {
1667 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_01, CFG_FILE_01_REG_LPCR_FREG_27M_90K);
1668 }
1669 }
1670
HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)1671 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)
1672 {
1673 MS_U32 u32Stamp = 0;
1674
1675 if(eFileEng >= TSP_TSIF_NUM)
1676 {
1677 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1678 return 0;
1679 }
1680
1681 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1682 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1683
1684 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_LPCR2_LOAD);
1685 u32Stamp = REG32_R(&RegFileCtrl[u8FileEng].CFG_FILE_12_13);
1686 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_LPCR2_LOAD);
1687
1688 return u32Stamp;
1689 }
1690
HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)1691 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)
1692 {
1693 if(eFileEng >= TSP_TSIF_NUM)
1694 {
1695 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1696 return 0;
1697 }
1698
1699 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1700 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1701
1702 return REG32_R(&RegFileCtrl[u8FileEng].CFG_FILE_14_15);
1703 }
1704
HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng,MS_PHY * pu32Addr)1705 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr)
1706 {
1707 if(eFileEng >= TSP_TSIF_NUM)
1708 {
1709 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1710 return;
1711 }
1712
1713 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1714 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1715
1716 *pu32Addr = (MS_PHY)(REG32_R(&RegFileCtrl[u8FileEng].CFG_FILE_16_17) & CFG_FILE_16_17_REG_TSP2MI_RADDR_TSIF_MASK);
1717 }
1718
HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1719 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1720 {
1721 if(eFileEng >= TSP_TSIF_NUM)
1722 {
1723 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FileIn Engine : 0x%x !!\n",__FUNCTION__,__LINE__,eFileEng));
1724 return;
1725 }
1726
1727 REG_FILE_ENG_Ctrl *RegFileCtrl = (eFileEng < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
1728 MS_U8 u8FileEng = (eFileEng < E_FILEENG_TSIF4)? eFileEng : (eFileEng - E_FILEENG_TSIF4);
1729
1730 if(bEnable)
1731 {
1732 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_WB_FSM_RESET);
1733 }
1734 else
1735 {
1736 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_00, CFG_FILE_00_REG_WB_FSM_RESET);
1737 }
1738 }
1739
HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng,MS_BOOL bEnable,MS_U32 u32Key)1740 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key)
1741 {
1742 // not support
1743 }
1744
HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)1745 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
1746 {
1747 switch (ePidFltSrc)
1748 {
1749 case E_TSP_PIDFLT_LIVE0:
1750 return TSP_PIDFLT_TSIF0;
1751 case E_TSP_PIDFLT_LIVE1:
1752 return TSP_PIDFLT_TSIF2;
1753 case E_TSP_PIDFLT_LIVE2:
1754 return TSP_PIDFLT_TSIF3;
1755 case E_TSP_PIDFLT_LIVE3:
1756 return TSP_PIDFLT_TSIF1;
1757 case E_TSP_PIDFLT_FILE0:
1758 return TSP_PIDFLT_TSIF1;
1759 case E_TSP_PIDFLT_FILE1:
1760 return TSP_PIDFLT_TSIF3;
1761 case E_TSP_PIDFLT_FILE2:
1762 return TSP_PIDFLT_TSIF0;
1763 case E_TSP_PIDFLT_FILE3:
1764 return TSP_PIDFLT_TSIF2;
1765 case E_TSP_PIDFLT_LIVE4:
1766 case E_TSP_PIDFLT_FILE4:
1767 return TSP_PIDFLT_TSIF4;
1768 case E_TSP_PIDFLT_LIVE5:
1769 case E_TSP_PIDFLT_FILE5:
1770 return TSP_PIDFLT_TSIF5;
1771 case E_TSP_PIDFLT_LIVE6:
1772 case E_TSP_PIDFLT_FILE6:
1773 return TSP_PIDFLT_TSIF6;
1774 default:
1775 printf("[TSP_ERR][%s][%d] Wrong filter source!!!\n",__FUNCTION__, __LINE__);
1776 break;
1777 }
1778
1779 return 0;
1780 }
1781
HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId,MS_U32 u32FltIn)1782 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn)
1783 {
1784 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
1785 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_IN_MASK) | ((u32FltIn << TSP_PIDFLT_TSIF_SHFT) & TSP_PIDFLT_IN_MASK));
1786 }
1787
HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId,MS_U32 u32FltOut)1788 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut)
1789 {
1790 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
1791 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_OUT_MASK)) | (u32FltOut & TSP_PIDFLT_OUT_MASK)));
1792 }
1793
HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId,MS_U32 u32SrcID)1794 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID)
1795 {
1796 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
1797 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_SRCID_MASK)) | ((u32SrcID << TSP_PIDFLT_SRCID_SHIFT) & TSP_PIDFLT_SRCID_MASK)));
1798 }
1799
HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId,MS_U32 u32SecFltId)1800 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId)
1801 {
1802 REG_PidFlt *pPidFlt = PPIDFLT2(fltId);
1803 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_SECFLT_MASK) | ((u32SecFltId << TSP_PIDFLT_SECFLT_SHFT) & TSP_PIDFLT_SECFLT_MASK));
1804 }
1805
HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId,MS_U32 u32PVREng,MS_BOOL bEn)1806 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn)
1807 {
1808 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
1809
1810 if(bEn)
1811 {
1812 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK) | (((1 << u32PVREng) << TSP_PIDFLT_PVRFLT_SHIFT) & TSP_PIDFLT_PVRFLT_MASK));
1813 }
1814 else
1815 {
1816 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK));
1817 }
1818 }
1819
HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId,MS_U8 u8Enable)1820 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable)
1821 {
1822 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
1823
1824 if(u8Enable)
1825 TSP32_IdrW(pPidFlt, TSP32_IdrR(pPidFlt) | (TSP_PID_FLT_PKTPUSH_PASS));
1826 else
1827 TSP32_IdrW(pPidFlt, TSP32_IdrR(pPidFlt) & ~(TSP_PID_FLT_PKTPUSH_PASS));
1828 }
1829
HAL_TSP_PidFlt_SetPid(MS_U32 fltId,MS_U32 u32Pid)1830 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32Pid)
1831 {
1832 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
1833 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PID_MASK) | ((u32Pid << TSP_PIDFLT_PID_SHFT) & TSP_PIDFLT_PID_MASK));
1834 }
1835
1836 //-------------------------------------------------------------------------------------------------
1837 // For section filter part
1838 //-------------------------------------------------------------------------------------------------
1839
HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)1840 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)
1841 {
1842 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN);
1843 REG16_MSK_W(&_RegCtrl->Hw_Config4, TSP_HW_DMA_MODE_MASK, (burstMode << TSP_HW_DMA_MODE_SHIFT));
1844 }
1845
HAL_TSP_SecFlt_SetType(REG_SecFlt * pSecFlt,MS_U32 u32FltType)1846 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType)
1847 {
1848 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_USER_MASK) | (u32FltType << TSP_SECFLT_USER_SHFT));
1849 }
1850
HAL_TSP_SecFlt_SetMode(REG_SecFlt * pSecFlt,MS_U32 u32SecFltMode)1851 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode)
1852 {
1853 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_MASK) | ((u32SecFltMode << TSP_SECFLT_MODE_SHFT) & TSP_SECFLT_MODE_MASK));
1854 }
1855
1856 // match mask --> 0 will compare
HAL_TSP_SecFlt_SetMask(REG_SecFlt * pSecFlt,MS_U8 * pu8Mask)1857 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask)
1858 {
1859 MS_U32 i,j;
1860 MS_U32 u32Temp;
1861
1862 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
1863 {
1864 j = (i << 2);
1865 u32Temp = (pu8Mask[j]) | (pu8Mask[j+ 1] << 8 ) | (pu8Mask[j+ 2] << 16 )| (pu8Mask[j+ 3] << 24);
1866 TSP32_IdrW((TSP32 *)&pSecFlt->Mask[i], u32Temp);
1867 }
1868 }
1869
1870 // not match mask --> 1 will compare
HAL_TSP_SecFlt_SetNMask(REG_SecFlt * pSecFlt,MS_U8 * pu8NMask)1871 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask)
1872 {
1873 MS_U32 i,j;
1874 MS_U32 u32Temp;
1875
1876 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
1877 {
1878 j = (i<< 2);
1879 u32Temp = (pu8NMask[j]) | (pu8NMask[j+ 1] << 8 ) | (pu8NMask[j+ 2] << 16 )| (pu8NMask[j+ 3] << 24);
1880 TSP32_IdrW((TSP32 *)&pSecFlt->NMask[i], u32Temp);
1881 }
1882 }
1883
HAL_TSP_SecFlt_SetMatch(REG_SecFlt * pSecFlt,MS_U8 * pu8Match)1884 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match)
1885 {
1886 MS_U32 i,j;
1887 MS_U32 u32Temp;
1888
1889 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
1890 {
1891 j = (i<< 2);
1892 u32Temp = (pu8Match[j]) | (pu8Match[j+ 1] << 8 ) | (pu8Match[j+ 2] << 16 )| (pu8Match[j+ 3] << 24);
1893 TSP32_IdrW((TSP32 *)&pSecFlt->Match[i], u32Temp);
1894 }
1895 }
1896
1897 //[LIMIT] Is impossible to identify the pidfilter is assigned a secfilter/buffer or not
HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt * pSecFlt,MS_U16 u16BufId)1898 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId)
1899 {
1900 TSP32_IdrW( &pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_SECBUF_MASK)
1901 | ((u16BufId << TSP_SECFLT_SECBUF_SHFT) & TSP_SECFLT_SECBUF_MASK) );
1902
1903 TSP32_IdrW( &pSecFlt->Ctrl_1, !!(u16BufId & 0x100));
1904 }
1905
HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt * pSecFlt)1906 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt)
1907 {
1908 MS_U16 u16RetVal = (TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_SECBUF_MASK) >> TSP_SECFLT_SECBUF_SHFT;
1909
1910 if(TSP32_IdrR(&pSecFlt->Ctrl_1) & TSP_SECFLT_SECBUF_H_MASK)
1911 {
1912 u16RetVal |= 0x100;
1913 }
1914
1915 return u16RetVal;
1916 }
1917
HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt * pPidFlt)1918 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt)
1919 {
1920 return (TSP32_IdrR(pPidFlt) & TSP_PIDFLT_OUT_MASK);
1921 }
1922
HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)1923 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)
1924 {
1925 // don't have to implement no reference
1926 }
1927
1928 // @FIXME: Is it secflt or secbuf?
HAL_TSP_SecFlt_ResetState(REG_SecFlt * pSecFlt)1929 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt)
1930 {
1931 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~(TSP_SECFLT_STATE_MASK));
1932 }
1933
HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt * pSecFlt)1934 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt)
1935 {
1936 TSP32_IdrW(&pSecFlt->Ctrl, 0);
1937 }
1938
HAL_TSP_SecFlt_GetState(REG_SecFlt * pSecFlt)1939 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt)
1940 {
1941 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_STATE_MASK) >> TSP_SECFLT_STATE_SHFT);
1942 }
1943
HAL_TSP_SecFlt_GetMode(REG_SecFlt * pSecFlt)1944 MS_U32 HAL_TSP_SecFlt_GetMode(REG_SecFlt *pSecFlt)
1945 {
1946 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_MODE_MASK) >> TSP_SECFLT_MODE_SHFT);
1947 }
1948
HAL_TSP_SecFlt_PcrReset(REG_SecFlt * pSecFlt)1949 void HAL_TSP_SecFlt_PcrReset(REG_SecFlt *pSecFlt)
1950 {
1951 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_PCRRST);
1952 }
1953
HAL_TSP_SecFlt_TryAlloc(REG_SecFlt * pSecFlt,MS_U16 u16TSPId)1954 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId)
1955 {
1956 MS_U32 reg;
1957
1958 // rmn counter doesn't need 32bit (check 13818) so we use some of it to store owner and alloc info
1959 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & (TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
1960 if (reg & TSP_SECFLT_ALLOC_MASK)
1961 {
1962 return FALSE;
1963 }
1964 reg |= TSP_SECFLT_ALLOC_MASK | ((u16TSPId<<TSP_SECFLT_OWNER_SHFT) & TSP_SECFLT_OWNER_MASK);
1965 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
1966
1967 return TRUE;
1968 }
1969
HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt * pSecFlt,MS_BOOL bSet)1970 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet)
1971 {
1972 if(bSet)
1973 {
1974 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_MODE_AUTO_CRCCHK);
1975 }
1976 else
1977 {
1978 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_AUTO_CRCCHK);
1979 }
1980 }
1981
HAL_TSP_SecFlt_Free(REG_SecFlt * pSecFlt)1982 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt)
1983 {
1984 MS_U32 reg;
1985
1986 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
1987 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
1988 }
1989
HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt * pSecFlt)1990 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt)
1991 {
1992 TSP32_IdrW(&pSecFlt->RmnCnt, TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECBUF_RMNCNT_MASK));
1993 }
1994
1995 //-------------------------------------------------------------------------------------------------
1996 // For section buffer part
1997 //-------------------------------------------------------------------------------------------------
HAL_TSP_SecBuf_SetBuf(REG_SecBuf * pSecBuf,MS_U32 u32StartAddr,MS_U32 u32BufSize)1998 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize)
1999 {
2000 // Check MIU select
2001 MS_U8 u8MiuSel;
2002 MS_PHY phyMiuOffsetSecBuf;
2003
2004 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetSecBuf, u32StartAddr);
2005 REG16_MSK_W(&_RegTopCtrl->CFG_TOP_09, CFG_TOP_09_REG_MIU_SEL_SEC_MASK, (u8MiuSel << CFG_TOP_09_REG_MIU_SEL_SEC_SHIFT));
2006 TSP32_IdrW(&pSecBuf->Start, phyMiuOffsetSecBuf);
2007 TSP32_IdrW(&pSecBuf->End, phyMiuOffsetSecBuf + u32BufSize);
2008 }
2009
HAL_TSP_SecBuf_SetRead(REG_SecBuf * pSecBuf,MS_U32 u32ReadAddr)2010 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr)
2011 {
2012 TSP32_IdrW(&pSecBuf->Read, u32ReadAddr);
2013 }
2014
HAL_TSP_SecBuf_GetStart(REG_SecBuf * pSecBuf)2015 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf)
2016 {
2017 return TSP32_IdrR(&pSecBuf->Start);
2018 }
2019
HAL_TSP_SecBuf_GetEnd(REG_SecBuf * pSecBuf)2020 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf)
2021 {
2022 return TSP32_IdrR(&pSecBuf->End);
2023 }
2024
HAL_TSP_SecBuf_GetBufCur(REG_SecBuf * pSecBuf)2025 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf)
2026 {
2027 //BufCur is control by firmware
2028 //we use Cur pointer to receive the newest data
2029 //and use write pointer to guarantee that the data between
2030 //read and write pointer is correct, so that user won't get
2031 //unverified data.
2032 return TSP32_IdrR(&pSecBuf->Cur);
2033 }
2034
HAL_TSP_SecBuf_Reset(REG_SecBuf * pSecBuf)2035 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf)
2036 {
2037 MS_U32 start;
2038
2039 start = TSP32_IdrR(&pSecBuf->Start);
2040
2041 TSP32_IdrW(&pSecBuf->Cur, start);
2042 TSP32_IdrW(&pSecBuf->Read, start);
2043 TSP32_IdrW(&pSecBuf->Write, start);
2044
2045 start = ( (MS_VIRT)pSecBuf - (MS_VIRT)REG_SECBUF_BASE ) / sizeof(REG_SecBuf) ;
2046 HAL_TSP_HCMD_BufRst(start); // @FIXME seems we don't need to do this
2047 }
2048
HAL_TSP_SecBuf_GetRead(REG_SecBuf * pSecBuf)2049 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf)
2050 {
2051 return TSP32_IdrR((TSP32*)&pSecBuf->Read);
2052 }
2053
HAL_TSP_SecBuf_GetWrite(REG_SecBuf * pSecBuf)2054 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf)
2055 {
2056 return TSP32_IdrR((TSP32*)&pSecBuf->Write);
2057 }
2058
HAL_TSP_SecBuf_TryAlloc(REG_SecBuf * pSecBuf,MS_U16 u16TSPId)2059 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId)
2060 {
2061 //@NOTE: K7U don't have to implement
2062 return TRUE;
2063 }
2064
HAL_TSP_SecBuf_Free(REG_SecBuf * pSecBuf)2065 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf)
2066 {
2067 // @TODO ref to HAL_TSP_SecBuf_TryAlloc
2068 TSP32_IdrW(&pSecBuf->Start, 0x0);
2069 }
2070
HAL_TSP_PidFlt_GetPid(REG_PidFlt * pPidFlt)2071 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt)
2072 {
2073 return ((TSP32_IdrR(pPidFlt) & TSP_PIDFLT_PID_MASK) >> TSP_PIDFLT_PID_SHFT);
2074 }
2075
HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId,MS_BOOL bEnable)2076 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable)
2077 {
2078 if(pcrFltId >= TSP_PCRFLT_NUM)
2079 {
2080 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2081 return;
2082 }
2083
2084 if(bEnable)
2085 {
2086 REG32_SET(&_RegPcrCtrl[pcrFltId].CFG_PCR_01_02, CFG_PCR_01_02_REG_PIDFLT_PCR_ENPCR);
2087 }
2088 else
2089 {
2090 REG32_CLR(&_RegPcrCtrl[pcrFltId].CFG_PCR_01_02, CFG_PCR_01_02_REG_PIDFLT_PCR_ENPCR);
2091 }
2092 }
2093
HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId,MS_U32 u32Pid)2094 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid)
2095 {
2096 if(pcrFltId >= TSP_PCRFLT_NUM)
2097 {
2098 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2099 return;
2100 }
2101
2102 REG32_MSK_W(&_RegPcrCtrl[pcrFltId].CFG_PCR_01_02, CFG_PCR_01_02_REG_PIDFLT_PCR_PID_MASK, u32Pid);
2103 }
2104
HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)2105 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)
2106 {
2107 if(pcrFltId >= TSP_PCRFLT_NUM)
2108 {
2109 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2110 return PVR_PIDFLT_DEF;
2111 }
2112
2113 return (REG32_R(&_RegPcrCtrl[pcrFltId].CFG_PCR_01_02) & CFG_PCR_01_02_REG_PIDFLT_PCR_PID_MASK);
2114 }
2115
HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId,TSP_PCR_SRC src)2116 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src)
2117 {
2118 if(pcrFltId >= TSP_PCRFLT_NUM)
2119 {
2120 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2121 return;
2122 }
2123
2124 REG16_MSK_W(&_RegPcrCtrl[pcrFltId].CFG_PCR_00, CFG_PCR_00_REG_PCR_SRC_MASK, src << CFG_PCR_00_REG_PCR_SRC_SHIFT);
2125 }
2126
HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId,MS_U32 u32SrcId)2127 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId)
2128 {
2129 if(pcrFltId >= TSP_PCRFLT_NUM)
2130 {
2131 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2132 return;
2133 }
2134
2135 REG32_MSK_W(&_RegPcrCtrl[pcrFltId].CFG_PCR_01_02, CFG_PCR_01_02_REG_PIDFLT_PCR_SOURCE_MASK, u32SrcId << CFG_PCR_01_02_REG_PIDFLT_PCR_SOURCE_SHIFT);
2136 }
2137
HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId,TSP_PCR_SRC * pPcrSrc)2138 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc)
2139 {
2140 if(pcrFltId >= TSP_PCRFLT_NUM)
2141 {
2142 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2143 *pPcrSrc = E_TSP_PCR_SRC_INVALID;
2144 return;
2145 }
2146
2147 *pPcrSrc = (REG16_R(&_RegPcrCtrl[pcrFltId].CFG_PCR_00) & CFG_PCR_00_REG_PCR_SRC_MASK) >> CFG_PCR_00_REG_PCR_SRC_SHIFT;
2148 }
2149
HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)2150 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
2151 {
2152 TSP_PCR_SRC ePcrSrc = E_TSP_PCR_SRC_INVALID;
2153 switch(ePidFltSrc)
2154 {
2155 case E_TSP_PIDFLT_LIVE0:
2156 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
2157 break;
2158 case E_TSP_PIDFLT_LIVE1:
2159 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
2160 break;
2161 case E_TSP_PIDFLT_LIVE2:
2162 ePcrSrc = E_TSP_PCR_SRC_TSIF3;
2163 break;
2164 case E_TSP_PIDFLT_LIVE3:
2165 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
2166 break;
2167 case E_TSP_PIDFLT_FILE0:
2168 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
2169 break;
2170 case E_TSP_PIDFLT_FILE1:
2171 ePcrSrc = E_TSP_PCR_SRC_TSIF3;
2172 break;
2173 case E_TSP_PIDFLT_FILE2:
2174 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
2175 break;
2176 case E_TSP_PIDFLT_FILE3:
2177 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
2178 break;
2179 case E_TSP_PIDFLT_LIVE4:
2180 case E_TSP_PIDFLT_FILE4:
2181 ePcrSrc = E_TSP_PCR_SRC_TSIF4;
2182 break;
2183 case E_TSP_PIDFLT_LIVE5:
2184 case E_TSP_PIDFLT_FILE5:
2185 ePcrSrc = E_TSP_PCR_SRC_TSIF5;
2186 break;
2187 case E_TSP_PIDFLT_LIVE6:
2188 case E_TSP_PIDFLT_FILE6:
2189 ePcrSrc = E_TSP_PCR_SRC_TSIF6;
2190 break;
2191 default:
2192 printf("[TSP_ERR][%s][%d] Wrong Flt Src type!!!\n",__FUNCTION__,__LINE__);
2193 break;
2194 }
2195 return ePcrSrc;
2196
2197 }
2198
HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId,MS_U32 * pu32Pcr_H,MS_U32 * pu32Pcr)2199 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr)
2200 {
2201 if(pcrFltId >= TSP_PCRFLT_NUM)
2202 {
2203 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2204 *pu32Pcr_H = 0;
2205 *pu32Pcr = 0;
2206 return;
2207 }
2208
2209 REG16_SET(&_RegPcrCtrl[pcrFltId].CFG_PCR_00, CFG_PCR_00_REG_PCR_READ);
2210 *pu32Pcr = REG32_R(&_RegPcrCtrl[pcrFltId].CFG_PCR_03_04);
2211 *pu32Pcr_H = REG16_R(&_RegPcrCtrl[pcrFltId].CFG_PCR_05) & CFG_PCR_05_REG_PCR_VALID_BIT32_MASK;
2212 REG16_CLR(&_RegPcrCtrl[pcrFltId].CFG_PCR_00, CFG_PCR_00_REG_PCR_READ);
2213 }
2214
HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)2215 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)
2216 {
2217 if(pcrFltId >= TSP_PCRFLT_NUM)
2218 {
2219 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2220 return;
2221 }
2222
2223 REG16_CLR(&_RegPcrCtrl[pcrFltId].CFG_PCR_00, CFG_PCR_00_REG_PCR_RESET);
2224 REG16_SET(&_RegPcrCtrl[pcrFltId].CFG_PCR_00, CFG_PCR_00_REG_PCR_RESET);
2225 }
2226
HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)2227 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)
2228 {
2229 switch(pcrFltId)
2230 {
2231 case 0:
2232 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR0_UPDATE_END);
2233 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR0_UPDATE_END);
2234 break;
2235 case 1:
2236 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR1_UPDATE_END);
2237 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR1_UPDATE_END);
2238 break;
2239 case 2:
2240 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR2_UPDATE_END);
2241 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR2_UPDATE_END);
2242 break;
2243 case 3:
2244 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR3_UPDATE_END);
2245 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR3_UPDATE_END);
2246 break;
2247 case 4:
2248 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR4_UPDATE_END);
2249 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR4_UPDATE_END);
2250 break;
2251 case 5:
2252 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR5_UPDATE_END);
2253 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR5_UPDATE_END);
2254 break;
2255 case 6:
2256 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR6_UPDATE_END);
2257 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR6_UPDATE_END);
2258 break;
2259 case 7:
2260 REG16_SET(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR7_UPDATE_END);
2261 REG16_CLR(&_RegCtrl->HwInt3_Stat,TSP_HWINT3_PCR7_UPDATE_END);
2262 break;
2263 default:
2264 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Eng ID : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2265 break;
2266 }
2267 }
2268
HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)2269 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)
2270 {
2271 if(pcrFltId >= TSP_PCRFLT_NUM)
2272 {
2273 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PCR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,pcrFltId));
2274 return 0;
2275 }
2276
2277 return (TSP_HWINT3_PCR0_UPDATE_END_EN << (pcrFltId + 16));
2278 }
2279
HAL_TSP_STC_Init(void)2280 void HAL_TSP_STC_Init(void)
2281 {
2282 /////////////Set STC control by HK////////////////
2283 // select synth from chip top : bit 1 -> 0 -> controlled by HK
2284 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
2285 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
2286 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC2_CW_SEL;
2287 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC3_CW_SEL;
2288 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~REG_CLKGEN1_STC4_CW_SEL;
2289 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~REG_CLKGEN1_STC5_CW_SEL;
2290 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~REG_CLKGEN1_STC6_CW_SEL;
2291 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~REG_CLKGEN1_STC7_CW_SEL;
2292
2293 // set HK STC synth CW
2294 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2295 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000;
2296 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800;
2297 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000;
2298 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = 0x2800;
2299 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = 0x0000;
2300 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = 0x2800;
2301 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = 0x0000;
2302 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = 0x2800;
2303 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC4_CW_L) = 0x0000;
2304 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC4_CW_H) = 0x2800;
2305 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC5_CW_L) = 0x0000;
2306 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC5_CW_H) = 0x2800;
2307 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC6_CW_L) = 0x0000;
2308 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC6_CW_H) = 0x2800;
2309 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC7_CW_L) = 0x0000;
2310 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC7_CW_H) = 0x2800;
2311
2312 // set STC synth
2313 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2314 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
2315 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2316 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
2317 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
2318 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
2319 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC2_CW_EN);
2320 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC2_CW_EN;
2321 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC2_CW_EN);
2322 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN);
2323 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC3_CW_EN;
2324 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN);
2325 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC4_CW_EN);
2326 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) |= REG_CLKGEN1_STC4_CW_EN;
2327 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC4_CW_EN);
2328 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC5_CW_EN);
2329 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) |= REG_CLKGEN1_STC5_CW_EN;
2330 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC5_CW_EN);
2331 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~(REG_CLKGEN1_STC6_CW_EN);
2332 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) |= REG_CLKGEN1_STC6_CW_EN;
2333 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~(REG_CLKGEN1_STC6_CW_EN);
2334 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~(REG_CLKGEN1_STC7_CW_EN);
2335 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) |= REG_CLKGEN1_STC7_CW_EN;
2336 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~(REG_CLKGEN1_STC7_CW_EN);
2337
2338 #if 0 // we don't use TSP CPU to control STC anymmore, so we don't have to do the following
2339 /////////////Set STC control by TSP////////////////
2340 // select synth from TSP : bit 1 -> 1 -> controlled by TSP
2341 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL;
2342 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL;
2343
2344 // set TSP STC synth CW
2345 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2346 TSP32_IdrW((TSP32 *)(0x0021024c<<1), 0x28000000);
2347 TSP32_IdrW((TSP32 *)(0x00210280<<1), 0x28000000); //STC1
2348
2349 // t2 , t3 had no 0x0021025c, it was add after t4, eanble synthesizer
2350 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x01);
2351 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x01);
2352 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x02); //STC1
2353 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x02);
2354 #endif
2355 }
2356
HAL_TSP_GetSTCSynth(MS_U32 Eng,MS_U32 * u32Sync)2357 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync)
2358 {
2359 switch (Eng)
2360 {
2361 case 0:
2362 // get HK STC synth CW
2363 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L);
2364 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ;
2365 break;
2366 case 1:
2367 // get HK STC synth CW
2368 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L);
2369 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) << 16 ;
2370 break;
2371 case 2:
2372 // get HK STC synth CW
2373 *u32Sync = TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L);
2374 *u32Sync |= TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) << 16 ;
2375 break;
2376 case 3:
2377 // get HK STC synth CW
2378 *u32Sync = TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L);
2379 *u32Sync |= TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) << 16 ;
2380 break;
2381 case 4:
2382 // get HK STC synth CW
2383 *u32Sync = TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC4_CW_L);
2384 *u32Sync |= TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC4_CW_H) << 16 ;
2385 break;
2386 case 5:
2387 // get HK STC synth CW
2388 *u32Sync = TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC5_CW_L);
2389 *u32Sync |= TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC5_CW_H) << 16 ;
2390 break;
2391 case 6:
2392 // get HK STC synth CW
2393 *u32Sync = TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC6_CW_L);
2394 *u32Sync |= TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC6_CW_H) << 16 ;
2395 break;
2396 case 7:
2397 // get HK STC synth CW
2398 *u32Sync = TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC7_CW_L);
2399 *u32Sync |= TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC7_CW_H) << 16 ;
2400 break;
2401 }
2402 }
2403
HAL_TSP_SetSTCSynth(MS_U32 Eng,MS_U32 u32Sync)2404 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync)
2405 {
2406 switch (Eng)
2407 {
2408 case 0:
2409 //set STC controller : HK or TSP CPU
2410 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
2411
2412 // set HK STC synth CW
2413 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF;
2414 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16;
2415
2416 // set STC synth : toggle update bit
2417 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2418 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
2419 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2420 break;
2421 case 1:
2422 //set STC controller : HK or TSP CPU
2423 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
2424
2425 // set HK STC synth CW
2426 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF;
2427 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = u32Sync >> 16;
2428
2429 // set STC synth : toggle update bit
2430 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
2431 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
2432 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
2433 break;
2434 case 2:
2435 //set STC controller : HK or TSP CPU
2436 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC2_CW_SEL;
2437
2438 // set HK STC synth CW
2439 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_L) = u32Sync & 0xFFFF;
2440 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC2_CW_H) = u32Sync >> 16;
2441
2442 // set STC synth : toggle update bit
2443 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC2_CW_EN);
2444 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC2_CW_EN;
2445 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC2_CW_EN);
2446 break;
2447 case 3:
2448 //set STC controller : HK or TSP CPU
2449 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~REG_CLKGEN2_STC3_CW_SEL;
2450
2451 // set HK STC synth CW
2452 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_L) = u32Sync & 0xFFFF;
2453 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_STC3_CW_H) = u32Sync >> 16;
2454
2455 // set STC synth : toggle update bit
2456 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN);
2457 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) |= REG_CLKGEN2_STC3_CW_EN;
2458 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYTNTH) &= ~(REG_CLKGEN2_STC3_CW_EN);
2459 break;
2460 case 4:
2461 //set STC controller : HK or TSP CPU
2462 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~REG_CLKGEN1_STC4_CW_SEL;
2463
2464 // set HK STC synth CW
2465 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC4_CW_L) = u32Sync & 0xFFFF;
2466 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC4_CW_H) = u32Sync >> 16;
2467
2468 // set STC synth : toggle update bit
2469 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC4_CW_EN);
2470 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) |= REG_CLKGEN1_STC4_CW_EN;
2471 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC4_CW_EN);
2472 break;
2473 case 5:
2474 //set STC controller : HK or TSP CPU
2475 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~REG_CLKGEN1_STC5_CW_SEL;
2476
2477 // set HK STC synth CW
2478 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC5_CW_L) = u32Sync & 0xFFFF;
2479 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_STC5_CW_H) = u32Sync >> 16;
2480
2481 // set STC synth : toggle update bit
2482 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC5_CW_EN);
2483 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) |= REG_CLKGEN1_STC5_CW_EN;
2484 TSP_CLKGEN1_REG(REG_CLKGEN1_DC0_SYTNTH) &= ~(REG_CLKGEN1_STC5_CW_EN);
2485 break;
2486 case 6:
2487 //set STC controller : HK or TSP CPU
2488 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~REG_CLKGEN1_STC6_CW_SEL;
2489
2490 // set HK STC synth CW
2491 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC6_CW_L) = u32Sync & 0xFFFF;
2492 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC6_CW_H) = u32Sync >> 16;
2493
2494 // set STC synth : toggle update bit
2495 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~(REG_CLKGEN1_STC6_CW_EN);
2496 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) |= REG_CLKGEN1_STC6_CW_EN;
2497 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~(REG_CLKGEN1_STC6_CW_EN);
2498 break;
2499 case 7:
2500 //set STC controller : HK or TSP CPU
2501 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~REG_CLKGEN1_STC7_CW_SEL;
2502
2503 // set HK STC synth CW
2504 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC7_CW_L) = u32Sync & 0xFFFF;
2505 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_STC7_CW_H) = u32Sync >> 16;
2506
2507 // set STC synth : toggle update bit
2508 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~(REG_CLKGEN1_STC7_CW_EN);
2509 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) |= REG_CLKGEN1_STC7_CW_EN;
2510 TSP_CLKGEN1_REG(REG_CLKGEN1_DC1_SYTNTH) &= ~(REG_CLKGEN1_STC7_CW_EN);
2511 break;
2512 }
2513 }
2514
HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)2515 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)
2516 {
2517 if (bEnable)
2518 {
2519 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
2520 }
2521 else
2522 {
2523 REG16_CLR(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
2524 }
2525 }
2526
HAL_TSP_STC64_Set(MS_U32 Eng,MS_U32 stcH,MS_U32 stcL)2527 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL)
2528 {
2529 switch (Eng)
2530 {
2531 case 0:
2532 REG32_W(&_RegCtrl->Pcr_L, stcL);
2533 REG32_W(&_RegCtrl->Pcr_H, stcH);
2534 break;
2535 case 1:
2536 REG32_W(&_RegCtrl->PCR64_2_L, stcL);
2537 REG32_W(&_RegCtrl->PCR64_2_H, stcH);
2538 break;
2539 default:
2540 if(Eng >= STC_ENG_NUM)
2541 {
2542 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong STC Engine : 0x%x !!\n",__FUNCTION__,__LINE__,Eng));
2543 return;
2544 }
2545
2546 MS_U32 u32SetBitMask = CFG_STC_19_1A_REG_SET_BASE_STC << ((Eng - 2) << 2);
2547
2548 REG32_W(&_RegStcCtrl->CFG_STC_00_17[Eng - 2].STC_L, stcL);
2549 REG32_W(&_RegStcCtrl->CFG_STC_00_17[Eng - 2].STC_H, stcH);
2550 REG32_SET(&_RegStcCtrl->CFG_STC_19_1A, u32SetBitMask);
2551 REG32_CLR(&_RegStcCtrl->CFG_STC_19_1A, u32SetBitMask);
2552 break;
2553 }
2554 }
2555
HAL_TSP_STC64_Get(MS_U32 Eng,MS_U32 * pStcH,MS_U32 * pStcL)2556 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL)
2557 {
2558 switch (Eng)
2559 {
2560 case 0:
2561 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
2562 *pStcH = REG32_R(&_RegCtrl->Pcr_H);
2563 *pStcL = REG32_R(&_RegCtrl->Pcr_L);
2564 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
2565 break;
2566 case 1:
2567 REG16_CLR(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
2568 *pStcH = REG32_R(&_RegCtrl->PCR64_2_H);
2569 *pStcL = REG32_R(&_RegCtrl->PCR64_2_L);
2570 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
2571 break;
2572 default:
2573 if(Eng >= STC_ENG_NUM)
2574 {
2575 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong STC Engine : 0x%x !!\n",__FUNCTION__,__LINE__,Eng));
2576 *pStcH = 0;
2577 *pStcL = 0;
2578 return;
2579 }
2580
2581 MS_U32 u32LdBitMask = CFG_STC_19_1A_REG_STC_LD << ((Eng - 2) << 2);
2582
2583 REG32_CLR(&_RegStcCtrl->CFG_STC_19_1A, u32LdBitMask);
2584 *pStcH = REG32_R(&_RegStcCtrl->CFG_STC_00_17[Eng - 2].STC_H);
2585 *pStcL = REG32_R(&_RegStcCtrl->CFG_STC_00_17[Eng - 2].STC_L);
2586 REG32_SET(&_RegStcCtrl->CFG_STC_19_1A, u32LdBitMask);
2587 break;
2588 }
2589 }
2590
HAL_TSP_STC33_CmdQSet(MS_U32 stcH,MS_U32 stcL)2591 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL)
2592 {
2593 // @TODO ask designer for the difference between 64bit STC and 33 Bit STC
2594 // and it's hw limit (like: cmdQ delay)
2595 REG16_W(&_RegCtrl->Pcr_H_CmdQ, stcH & TSP_REG_PCR_CMDQ_H);
2596 REG32_W(&_RegCtrl->Pcr_L_CmdQ, stcL);
2597 }
2598
HAL_TSP_STC33_CmdQGet(MS_U32 * pStcH,MS_U32 * pStcL)2599 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL)
2600 {
2601 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
2602 *pStcH = REG16_R(&_RegCtrl->Pcr_H_CmdQ) & TSP_REG_PCR_CMDQ_H;
2603 *pStcL = REG32_R(&_RegCtrl->Pcr_L_CmdQ);
2604 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
2605 }
2606
HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType,MS_U32 pktDmxId)2607 void HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType, MS_U32 pktDmxId)
2608 {
2609 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2610 {
2611 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2612
2613 REG16_MSK_W(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_INPUT_SRC_MASK, ((MS_U16)pktDmxId) << CFG_AV_02_REG_INPUT_SRC_SHIFT);
2614 }
2615 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2616 {
2617 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2618
2619 REG16_MSK_W(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_INPUT_SRC_MASK, ((MS_U16)pktDmxId) << CFG_AV_02_REG_INPUT_SRC_SHIFT);
2620 }
2621 else
2622 {
2623 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2624 }
2625 }
2626
HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType,TSP_SRC_SEQ * pktDmxId)2627 void HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId)
2628 {
2629 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2630 {
2631 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2632
2633 *pktDmxId = ((REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02)) & CFG_AV_02_REG_INPUT_SRC_MASK) >> CFG_AV_02_REG_INPUT_SRC_SHIFT;
2634 }
2635 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2636 {
2637 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2638
2639 *pktDmxId = ((REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02)) & CFG_AV_02_REG_INPUT_SRC_MASK) >> CFG_AV_02_REG_INPUT_SRC_SHIFT;
2640 }
2641 else
2642 {
2643 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2644 *pktDmxId = E_TSP_SRC_INVALID;
2645 }
2646 }
2647
HAL_TSP_FIFO_BD_AUD_En(TSP_DST_SEQ eAudioType,MS_BOOL bMainChEn,MS_BOOL bEn)2648 void HAL_TSP_FIFO_BD_AUD_En(TSP_DST_SEQ eAudioType, MS_BOOL bMainChEn, MS_BOOL bEn)
2649 {
2650 if((eAudioType >= E_TSP_DST_FIFO_AUDIO) && (eAudioType <= E_TSP_DST_FIFO_AUDIO6))
2651 {
2652 MS_U8 u8AudioFltIdx = eAudioType - E_TSP_DST_FIFO_AUDIO;
2653
2654 if(bEn)
2655 {
2656 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_REG_BD_AUD_EN);
2657
2658 if(bMainChEn)
2659 {
2660 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_REG_MAIN_CHANNEL);
2661 }
2662 else
2663 {
2664 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_REG_MAIN_CHANNEL);
2665 }
2666 }
2667 else
2668 {
2669 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_REG_BD_AUD_EN);
2670 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_REG_MAIN_CHANNEL);
2671 }
2672 }
2673 else
2674 {
2675 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2676 }
2677 }
2678
HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn)2679 void HAL_TSP_BD_AUD_En(MS_U32 u32BD, MS_BOOL bEn)
2680 {
2681 if(bEn)
2682 {
2683 switch(u32BD)
2684 {
2685 case 0:
2686 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO, TRUE, TRUE);
2687 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO2, FALSE, TRUE);
2688 break;
2689 case 1:
2690 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO3, TRUE, TRUE);
2691 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO4, FALSE, TRUE);
2692 break;
2693 case 2:
2694 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO5, TRUE, TRUE);
2695 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO6, FALSE, TRUE);
2696 break;
2697 default:
2698 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2699 break;
2700 }
2701 }
2702 else
2703 {
2704 switch(u32BD)
2705 {
2706 case 0:
2707 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO, FALSE, FALSE);
2708 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO2, FALSE, FALSE);
2709 break;
2710 case 1:
2711 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO3, FALSE, FALSE);
2712 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO4, FALSE, FALSE);
2713 break;
2714 case 2:
2715 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO5, FALSE, FALSE);
2716 HAL_TSP_FIFO_BD_AUD_En(E_TSP_DST_FIFO_AUDIO6, FALSE, FALSE);
2717 break;
2718 default:
2719 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2720 break;
2721 }
2722 }
2723 }
2724
2725 #if FPGA_TEST
2726
HAL_TSP_FIFO_ClearAll()2727 void HAL_TSP_FIFO_ClearAll()
2728 {
2729 // clear ALL FIFO !!!
2730 MS_U8 u8Idx = 0;
2731
2732 for(u8Idx = 0; u8Idx < E_TSP_HAL_CAP_VAL_AFIFO_NUM; u8Idx++)
2733 {
2734 REG16_CLR(&_RegAudioCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_PS_MODE);
2735 }
2736
2737 for(u8Idx = 0; u8Idx < E_TSP_HAL_CAP_VAL_VFIFO_NUM; u8Idx++)
2738 {
2739 REG16_CLR(&_RegVideoCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_PS_MODE);
2740 }
2741 }
2742
HAL_TSP_FIFO_ReadEn(TSP_DST_SEQ eFltType,MS_BOOL bEn)2743 void HAL_TSP_FIFO_ReadEn(TSP_DST_SEQ eFltType, MS_BOOL bEn)
2744 {
2745 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2746 {
2747 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2748
2749 if(bEn)
2750 {
2751 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_06, CFG_AV_06_REG_PES_RSEL);
2752 }
2753 else
2754 {
2755 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_06, CFG_AV_06_REG_PES_RSEL);
2756 }
2757 }
2758 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2759 {
2760 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2761
2762 if(bEn)
2763 {
2764 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_06, CFG_AV_06_REG_PES_RSEL);
2765 }
2766 else
2767 {
2768 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_06, CFG_AV_06_REG_PES_RSEL);
2769 }
2770 }
2771 else
2772 {
2773 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2774 }
2775 }
2776
HAL_TSP_FIFO_ReadPkt(TSP_DST_SEQ eFltType)2777 MS_U16 HAL_TSP_FIFO_ReadPkt(TSP_DST_SEQ eFltType)
2778 {
2779 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2780 {
2781 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2782
2783 return REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_07) & CFG_AV_07_REG_DEBUG_FIFO_DATA_MASK;
2784 }
2785 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2786 {
2787 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2788
2789 return REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_07) & CFG_AV_07_REG_DEBUG_FIFO_DATA_MASK;
2790 }
2791 else
2792 {
2793 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2794 return 0;
2795 }
2796 }
2797
HAL_TSP_FIFO_Connect(TSP_DST_SEQ eFltType,MS_BOOL bEn)2798 void HAL_TSP_FIFO_Connect(TSP_DST_SEQ eFltType, MS_BOOL bEn)
2799 {
2800 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2801 {
2802 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2803
2804 if(bEn)
2805 {
2806 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_06, CFG_AV_06_REG_FIFO_RD);
2807 }
2808 else
2809 {
2810 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_06, CFG_AV_06_REG_FIFO_RD);
2811 }
2812 }
2813 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2814 {
2815 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2816
2817 if(bEn)
2818 {
2819 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_06, CFG_AV_06_REG_FIFO_RD);
2820 }
2821 else
2822 {
2823 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_06, CFG_AV_06_REG_FIFO_RD);
2824 }
2825 }
2826 else
2827 {
2828 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2829 }
2830 }
2831
HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)2832 MS_U32 HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)
2833 {
2834 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2835 {
2836 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2837
2838 return REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_08) & CFG_AV_08_REG_PID_MATCH_MASK;
2839 }
2840 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2841 {
2842 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2843
2844 return REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_08) & CFG_AV_08_REG_PID_MATCH_MASK;
2845 }
2846 else
2847 {
2848 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2849 return PVR_PIDFLT_DEF;
2850 }
2851 }
2852
HAL_TSP_TRACE_MARK_En(TSP_DST_SEQ eFltType,MS_BOOL bEn)2853 void HAL_TSP_TRACE_MARK_En(TSP_DST_SEQ eFltType,MS_BOOL bEn)
2854 {
2855 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2856 {
2857 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2858
2859 if(bEn)
2860 {
2861 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_TRACE_MARK_EN);
2862 }
2863 else
2864 {
2865 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_TRACE_MARK_EN);
2866 }
2867 }
2868 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2869 {
2870 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2871
2872 if(bEn)
2873 {
2874 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_TRACE_MARK_EN);
2875 }
2876 else
2877 {
2878 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_TRACE_MARK_EN);
2879 }
2880 }
2881 else
2882 {
2883 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2884 }
2885 }
2886
2887 #endif
2888
2889 //@NOTE for TS mode
2890 //@TODO need to rename (TS enable or PKTDMX_BYPASS)
HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)2891 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn)
2892 {
2893 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2894 {
2895 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2896
2897 if(bEn)
2898 {
2899 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PID_BYPASS);
2900 }
2901 else
2902 {
2903 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PID_BYPASS);
2904 }
2905 }
2906 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2907 {
2908 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2909
2910 if(bEn)
2911 {
2912 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PID_BYPASS);
2913 }
2914 else
2915 {
2916 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PID_BYPASS);
2917 }
2918 }
2919 else
2920 {
2921 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2922 }
2923 }
2924
2925 //PS MODE
2926 //NEED TO rename
HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)2927 void HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn) // @NOTE this function only for Tsif0 fileEng other fileEng has no by pass capability
2928 {
2929 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2930 {
2931 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2932
2933 if(bEn)
2934 {
2935 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE);
2936 }
2937 else
2938 {
2939 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE);
2940 }
2941 }
2942 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2943 {
2944 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2945
2946 if(bEn)
2947 {
2948 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE);
2949 }
2950 else
2951 {
2952 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE);
2953 }
2954 }
2955 else
2956 {
2957 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2958 }
2959 }
2960
HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng,TSP_DST_SEQ eFltType)2961 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType)
2962 {
2963 // (K6 HW CL)
2964 // PS mode source sel need to be independent
2965 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2966 {
2967 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2968
2969 REG16_MSK_W(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_01, CFG_AV_01_REG_PS_MODE_SRC_MASK, ((eFileEng + 1) << CFG_AV_01_REG_PS_MODE_SRC_SHIFT));
2970 }
2971 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2972 {
2973 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
2974
2975 REG16_MSK_W(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_01, CFG_AV_01_REG_PS_MODE_SRC_MASK, ((eFileEng + 1) << CFG_AV_01_REG_PS_MODE_SRC_SHIFT));
2976 }
2977 else
2978 {
2979 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
2980 }
2981 }
2982
HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType,MS_BOOL bReset)2983 void HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType, MS_BOOL bReset)
2984 {
2985 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
2986 {
2987 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
2988
2989 if(bReset)
2990 {
2991 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_01, CFG_AV_01_REG_RESET_FIFO_PARSER);
2992 }
2993 else
2994 {
2995 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_01, CFG_AV_01_REG_RESET_FIFO_PARSER);
2996 }
2997 }
2998 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
2999 {
3000 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
3001
3002 if(bReset)
3003 {
3004 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_01, CFG_AV_01_REG_RESET_FIFO_PARSER);
3005 }
3006 else
3007 {
3008 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_01, CFG_AV_01_REG_RESET_FIFO_PARSER);
3009 }
3010 }
3011 else
3012 {
3013 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
3014 }
3015
3016 _delay(1);
3017 }
3018
HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)3019 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)
3020 {
3021 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
3022 {
3023 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
3024
3025 if(bSkip)
3026 {
3027 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_MASK_SCR_EN);
3028 }
3029 else
3030 {
3031 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_MASK_SCR_EN);
3032 }
3033 }
3034 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
3035 {
3036 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
3037
3038 if(bSkip)
3039 {
3040 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_MASK_SCR_EN);
3041 }
3042 else
3043 {
3044 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_MASK_SCR_EN);
3045 }
3046 }
3047 else
3048 {
3049 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
3050 }
3051 }
3052
HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType,MS_BOOL bDisable)3053 void HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType, MS_BOOL bDisable)
3054 {
3055 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
3056 {
3057 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
3058
3059 if(bDisable)
3060 {
3061 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_BLOCK_DISABLE);
3062 }
3063 else
3064 {
3065 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_BLOCK_DISABLE);
3066 }
3067 }
3068 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
3069 {
3070 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
3071
3072 if(bDisable)
3073 {
3074 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_BLOCK_DISABLE);
3075 }
3076 else
3077 {
3078 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_BLOCK_DISABLE);
3079 }
3080 }
3081 else
3082 {
3083 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
3084 }
3085 }
3086
HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)3087 MS_BOOL HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)
3088 {
3089 MS_U16 u16Matched = 0;
3090
3091 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
3092 {
3093 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
3094
3095 u16Matched = REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_01) & CFG_AV_01_REG_RESET_FIFO_PARSER;
3096 }
3097 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
3098 {
3099 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
3100
3101 u16Matched = REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_01) & CFG_AV_01_REG_RESET_FIFO_PARSER;
3102 }
3103 else
3104 {
3105 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
3106 return FALSE;
3107 }
3108
3109 return (u16Matched) ? TRUE: FALSE;
3110 }
3111
HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)3112 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)
3113 {
3114 #define E_TSP_FIFO_STATUS_ISRESET 0x80000000
3115 #define E_TSP_FIFO_STATUS_EMPTY 0x00000001
3116 #define E_TSP_FIFO_STATUS_OVERFLOW 0x00000002
3117 #define E_TSP_FIFO_STATUS_LEVEL 0x0000000C
3118 #define TSP_FIFO_STATUS_LEVEL_SHFT 2 //shift the value get from HAL_TSP_FIFO_Level to the u32Status level position
3119 // @NOTE please follow K2 like series to return this value
3120 // since API layer didn't define for each column
3121 // we only defined that 0x80000000 stands for this fifo reset is High
3122 // 0x00000001 stands for this fifo is empty
3123 // 0x00000002 stands for this fifo is overflow
3124 // 0x0000000C is a mask for this fifo level
3125 // this is exclusive usage
3126 MS_U32 u32Status = 0;
3127 if (HAL_TSP_FIFO_IsReset(eFltType))
3128 {
3129 u32Status |= E_TSP_FIFO_STATUS_ISRESET;
3130 }
3131 if (HAL_TSP_FIFO_Empty(eFltType))
3132 {
3133 u32Status |= E_TSP_FIFO_STATUS_EMPTY;
3134 }
3135 if (HAL_TSP_FIFO_Overflow(eFltType))
3136 {
3137 u32Status |= E_TSP_FIFO_STATUS_OVERFLOW;
3138 }
3139
3140 u32Status |= ((HAL_TSP_FIFO_Level(eFltType)<<TSP_FIFO_STATUS_LEVEL_SHFT)&E_TSP_FIFO_STATUS_LEVEL);
3141
3142 return u32Status;
3143 }
3144
HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)3145 MS_U32 HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)
3146 {
3147 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
3148 {
3149 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
3150
3151 return (REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_06) & CFG_AV_06_REG_FIFO_WR_LEVEL_MASK) >> CFG_AV_06_REG_FIFO_WR_LEVEL_SHIFT;
3152 }
3153 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
3154 {
3155 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
3156
3157 return (REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_06) & CFG_AV_06_REG_FIFO_WR_LEVEL_MASK) >> CFG_AV_06_REG_FIFO_WR_LEVEL_SHIFT;
3158 }
3159 else
3160 {
3161 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
3162 return 0;
3163 }
3164 }
3165
HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)3166 MS_BOOL HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)
3167 {
3168 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
3169 {
3170 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
3171
3172 return (REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_06) & CFG_AV_06_REG_FIFO_FULL_MASK) >> CFG_AV_06_REG_FIFO_FULL_SHIFT;
3173 }
3174 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
3175 {
3176 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
3177
3178 return (REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_06) & CFG_AV_06_REG_FIFO_FULL_MASK) >> CFG_AV_06_REG_FIFO_FULL_SHIFT;
3179 }
3180 else
3181 {
3182 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
3183 return FALSE;
3184 }
3185 }
3186
HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)3187 MS_BOOL HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)
3188 {
3189 if((eFltType >= E_TSP_DST_FIFO_AUDIO) && (eFltType <= E_TSP_DST_FIFO_AUDIO6))
3190 {
3191 MS_U8 u8AudioFltIdx = eFltType - E_TSP_DST_FIFO_AUDIO;
3192
3193 return (REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_06) & CFG_AV_06_REG_FIFO_EMPTY_MASK) >> CFG_AV_06_REG_FIFO_EMPTY_SHIFT;
3194 }
3195 else if(eFltType <= E_TSP_DST_FIFO_VIDEO8)
3196 {
3197 MS_U8 u8VideoFltIdx = eFltType - E_TSP_DST_FIFO_VIDEO;
3198
3199 return (REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_06) & CFG_AV_06_REG_FIFO_EMPTY_MASK) >> CFG_AV_06_REG_FIFO_EMPTY_SHIFT;
3200 }
3201 else
3202 {
3203 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
3204 return FALSE;
3205 }
3206 }
3207
_HAL_TSP_VQ_TxConfig(void)3208 static MS_BOOL _HAL_TSP_VQ_TxConfig(void)
3209 {
3210 // reg_vq_wr_threshold = 0x8
3211 // reg_vq_forcefire_cnt_1k= 0xC
3212 REG16_MSK_W(&_RegOtherCtrl->CFG_OTHER_70, CFG_OTHER_70_REG_VQ_WR_THRESHOLD_MASK, (0x8 << CFG_OTHER_70_REG_VQ_WR_THRESHOLD_SHIFT));
3213 REG16_MSK_W(&_RegOtherCtrl->CFG_OTHER_70, CFG_OTHER_70_REG_VQ_FORCEFIRE_CNT_1K_MASK, (0xC << CFG_OTHER_70_REG_VQ_FORCEFIRE_CNT_1K_SHIFT));
3214
3215 return TRUE;
3216 }
3217
HAL_TSP_SetVQ(MS_PHYADDR u32BaseAddr,MS_U32 u32BufLen)3218 MS_BOOL HAL_TSP_SetVQ(MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen)
3219 {
3220 MS_U32 vqId = 0;
3221 MS_U32 u32VQ_PktNum = 0;
3222 MS_U32 u32Addr = 0;
3223 MS_U32 u32OneBufSize = 0;
3224
3225 // Check MIU select
3226 MS_U8 u8MiuSel = 0;
3227
3228 _phy_to_miu_offset(u8MiuSel, u32Addr, u32BaseAddr);
3229 REG16_MSK_W(&_RegTopCtrl->CFG_TOP_09, CFG_TOP_09_REG_MIU_SEL_VQ_MASK, (u8MiuSel << CFG_TOP_09_REG_MIU_SEL_VQ_SHIFT));
3230
3231 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment
3232 u32VQ_PktNum = u32OneBufSize / VQ_PACKET_UNIT_LEN;
3233
3234 _HAL_TSP_VQ_TxConfig();
3235
3236 for(vqId = 0; vqId < VQ_NUM; vqId ++)
3237 {
3238 // in kaiser we needs to set 6 VQ and the base unit is 208 so total vq size should be N*208*6
3239 if (TRUE != HAL_TSP_VQ_Buffer(vqId, u32Addr, u32VQ_PktNum))
3240 {
3241 return FALSE;
3242 }
3243 u32Addr += u32OneBufSize;
3244 }
3245
3246 HAL_TSP_VQ_Enable(TRUE);
3247 return TRUE;
3248 }
3249
HAL_TSP_VQ_Buffer(MS_U32 vqId,MS_PHYADDR u32BaseAddr,MS_U32 u32VQ_PktNum)3250 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32VQ_PktNum)
3251 {
3252 if(vqId >= VQ_NUM)
3253 {
3254 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong VQ Engine : 0x%x !!\n",__FUNCTION__,__LINE__,vqId));
3255 return FALSE;
3256 }
3257
3258 REG32_W(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_base, (u32BaseAddr >> MIU_BUS));
3259 REG16_W(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_size_208byte, u32VQ_PktNum);
3260
3261 return TRUE;
3262 }
3263
HAL_TSP_VQ_Enable(MS_BOOL bEn)3264 void HAL_TSP_VQ_Enable(MS_BOOL bEn)
3265 {
3266 if (bEn)
3267 {
3268 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
3269 }
3270 else
3271 {
3272 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
3273 }
3274 }
3275
HAL_TSP_VQ_Reset(MS_U32 vqId,MS_BOOL bEn)3276 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn)
3277 {
3278 if(vqId >= VQ_NUM)
3279 {
3280 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong VQ Engine : 0x%x !!\n",__FUNCTION__,__LINE__,vqId));
3281 return;
3282 }
3283
3284 if(bEn)
3285 {
3286 REG16_SET(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_RESET);
3287 }
3288 else
3289 {
3290 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_RESET);
3291 }
3292 }
3293
3294 #if FPGA_TEST
3295
HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis)3296 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId, MS_BOOL bDis)
3297 {
3298 if(vqId >= VQ_NUM)
3299 {
3300 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong VQ Engine : 0x%x !!\n",__FUNCTION__,__LINE__,vqId));
3301 return FALSE;
3302 }
3303
3304 if(bDis)
3305 {
3306 REG16_SET(&_RegOtherCtrl->CFG_OTHER_75, (CFG_OTHER_75_REG_VQ_TX_BLOCK_DISABLE << vqId));
3307 }
3308 else
3309 {
3310 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_75, (CFG_OTHER_75_REG_VQ_TX_BLOCK_DISABLE << vqId));
3311 }
3312
3313 return TRUE;
3314 }
3315
HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId,MS_BOOL bEn)3316 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn)
3317 {
3318 if(vqId >= VQ_NUM)
3319 {
3320 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong VQ Engine : 0x%x !!\n",__FUNCTION__,__LINE__,vqId));
3321 return;
3322 }
3323
3324 if(bEn)
3325 {
3326 REG16_SET(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_OVERFLOW_INT_EN);
3327 }
3328 else
3329 {
3330 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_OVERFLOW_INT_EN);
3331 }
3332 }
3333
HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId)3334 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId)
3335 {
3336 if(vqId >= VQ_NUM)
3337 {
3338 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong VQ Engine : 0x%x !!\n",__FUNCTION__,__LINE__,vqId));
3339 return;
3340 }
3341
3342 REG16_SET(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_CLR_OVERFLOW_INT);
3343 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_ctrl, REG_OTHER_VQ_TX_REG_VQ_CLR_OVERFLOW_INT);
3344 }
3345
3346 #endif
3347
HAL_PVR_Init(MS_U32 u32PVREng,MS_U32 pktDmxId)3348 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId)
3349 {
3350 if(u32PVREng >= TSP_PVRENG_NUM)
3351 {
3352 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3353 return;
3354 }
3355
3356 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3357 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3358
3359 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_PINGPONG_EN);
3360 REG16_MSK_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_10, CFG_PVR_10_REG_INPUT_SRC_MASK, (((MS_U16)pktDmxId) << CFG_PVR_10_REG_INPUT_SRC_SHIFT));
3361 }
3362
HAL_PVR_Exit(MS_U32 u32PVREng)3363 void HAL_PVR_Exit(MS_U32 u32PVREng)
3364 {
3365 if(u32PVREng >= TSP_PVRENG_NUM)
3366 {
3367 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3368 return;
3369 }
3370
3371 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3372 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3373
3374 //reset pvr control registers
3375 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_PINGPONG_EN);
3376 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_10, CFG_PVR_10_REG_INPUT_SRC_MASK);
3377
3378 //reset write address
3379 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_RST_WADR);
3380 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_RST_WADR);
3381
3382 //reset time-stamp
3383 HAL_PVR_SetPVRTimeStamp(u32PVREng, 0);
3384 }
3385
HAL_PVR_Start(MS_U32 u32PVREng)3386 void HAL_PVR_Start(MS_U32 u32PVREng)
3387 {
3388 if(u32PVREng >= TSP_PVRENG_NUM)
3389 {
3390 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3391 return;
3392 }
3393
3394 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3395 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3396
3397 //reset write address
3398 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_RST_WADR);
3399 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_RST_WADR);
3400
3401 //enable string to miu
3402 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_EN);
3403 }
3404
HAL_PVR_Stop(MS_U32 u32PVREng)3405 void HAL_PVR_Stop(MS_U32 u32PVREng)
3406 {
3407 if(u32PVREng >= TSP_PVRENG_NUM)
3408 {
3409 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3410 return;
3411 }
3412
3413 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3414 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3415
3416 //disable string to miu
3417 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_EN);
3418 }
3419
HAL_PVR_Pause(MS_U32 u32PVREng,MS_BOOL bPause)3420 void HAL_PVR_Pause(MS_U32 u32PVREng, MS_BOOL bPause)
3421 {
3422 if(u32PVREng >= TSP_PVRENG_NUM)
3423 {
3424 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3425 return;
3426 }
3427
3428 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3429 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3430
3431 if(bPause)
3432 {
3433 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_PAUSE);
3434 }
3435 else
3436 {
3437 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_STR2MI_PAUSE);
3438 }
3439 }
3440
HAL_PVR_RecPid(MS_U32 u32PVREng,MS_BOOL bSet)3441 void HAL_PVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet)
3442 {
3443 if(u32PVREng >= TSP_PVRENG_NUM)
3444 {
3445 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3446 return;
3447 }
3448
3449 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3450 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3451
3452 if(bSet)
3453 {
3454 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_RECORD_ALL);
3455 }
3456 else
3457 {
3458 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_RECORD_ALL);
3459 }
3460 }
3461
3462 #if FPGA_TEST
3463
HAL_PVR_Alignment_Enable(MS_U32 u32PVREng,MS_BOOL bEnable)3464 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable)
3465 {
3466 if(u32PVREng >= TSP_PVRENG_NUM)
3467 {
3468 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3469 return;
3470 }
3471
3472 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3473 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3474
3475 if(bEnable)
3476 {
3477 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_ALIGN_EN);
3478 }
3479 else
3480 {
3481 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_ALIGN_EN);
3482 }
3483 }
3484
HAL_PVR_FlushData(MS_U32 u32PVREng)3485 void HAL_PVR_FlushData(MS_U32 u32PVREng)
3486 {
3487 if(u32PVREng >= TSP_PVRENG_NUM)
3488 {
3489 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3490 return;
3491 }
3492
3493 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3494 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3495
3496 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_FLUSH_PVR_DATA);
3497 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_FLUSH_PVR_DATA);
3498 }
3499
HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)3500 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng, MS_BOOL bSkip)
3501 {
3502 if(u32PVREng >= TSP_PVRENG_NUM)
3503 {
3504 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3505 return;
3506 }
3507
3508 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3509 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3510
3511 if(bSkip)
3512 {
3513 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_MASK_SCR_PVR_EN);
3514 }
3515 else
3516 {
3517 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_MASK_SCR_PVR_EN);
3518 }
3519 }
3520
HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)3521 void HAL_PVR_Block_Dis(MS_U32 u32PVREng, MS_BOOL bDisable)
3522 {
3523 if(u32PVREng >= TSP_PVRENG_NUM)
3524 {
3525 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3526 return;
3527 }
3528
3529 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3530 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3531
3532 if(bDisable)
3533 {
3534 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_PVR_BLOCK_DISABLE);
3535 }
3536 else
3537 {
3538 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_PVR_BLOCK_DISABLE);
3539 }
3540 }
3541
HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)3542 void HAL_PVR_BurstLen(MS_U32 u32PVREng, MS_U16 u16BurstMode)
3543 {
3544 if(u32PVREng >= TSP_PVRENG_NUM)
3545 {
3546 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3547 return;
3548 }
3549
3550 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3551 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3552
3553 REG16_MSK_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_BURST_LEN_MASK, (u16BurstMode << CFG_PVR_00_REG_PVR_BURST_LEN_SHIFT));
3554 }
3555
HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId,MS_BOOL bEnable)3556 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId, MS_BOOL bEnable)
3557 {
3558 // not support
3559 }
3560
HAL_PVR_MOBF_Enable(MS_U32 u32PVREng,MS_BOOL bEnable,MS_U32 u32Key)3561 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key)
3562 {
3563 // not support
3564 }
3565
HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng,MS_BOOL bLocal_Stream)3566 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream)
3567 {
3568 if (u32PVREng >= TSP_PVRENG_NUM)
3569 {
3570 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3571 return;
3572 }
3573
3574 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3575 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3576
3577 if (bLocal_Stream) //Stream
3578 {
3579 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_PVR_TIMESTAMP_SRC_SEL);
3580 }
3581 else //local
3582 {
3583 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_PVR_TIMESTAMP_SRC_SEL);
3584 }
3585 }
3586
HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng,MS_U32 u32Stamp)3587 void HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng , MS_U32 u32Stamp)
3588 {
3589 // not supported
3590 }
3591
HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)3592 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)
3593 {
3594 if (u32PVREng >= TSP_PVRENG_NUM)
3595 {
3596 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3597 return;
3598 }
3599
3600 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3601 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3602
3603 // bypass_timestamp_sel: 1 , timestamp don't need to consider PVR pause time
3604 // 0 , timestamp needs to consider PVR pause time
3605 if(bEnable)
3606 {
3607 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_26, CFG_PVR_26_REG_BYPASS_TIMESTAMP_SEL);
3608 }
3609 else
3610 {
3611 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_26, CFG_PVR_26_REG_BYPASS_TIMESTAMP_SEL);
3612 }
3613 }
3614
HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime)3615 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng, MS_U32 u32PauseTime)
3616 {
3617 if (u32PVREng >= TSP_PVRENG_NUM)
3618 {
3619 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3620 return;
3621 }
3622
3623 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3624 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3625
3626 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_22_23, u32PauseTime);
3627 }
3628
HAL_PVR_RecNull(MS_U32 u32PVREng,MS_BOOL bSet)3629 void HAL_PVR_RecNull(MS_U32 u32PVREng, MS_BOOL bSet)
3630 {
3631 if(u32PVREng >= TSP_PVRENG_NUM)
3632 {
3633 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3634 return;
3635 }
3636
3637 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3638 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3639
3640 if(bSet)
3641 {
3642 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_DIS_NULL_PKT);
3643 }
3644 else
3645 {
3646 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_20, CFG_PVR_20_REG_DIS_NULL_PKT);
3647 }
3648 }
3649
HAL_PVR_SetBuf(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32BufSize0,MS_U32 u32StartAddr1,MS_U32 u32BufSize1)3650 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1)
3651 {
3652 if(u32PVREng >= TSP_PVRENG_NUM)
3653 {
3654 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3655 return;
3656 }
3657
3658 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3659 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3660
3661 MS_U32 u32EndAddr0 = u32StartAddr0 + u32BufSize0;
3662 MS_U32 u32EndAddr1 = u32StartAddr1 + u32BufSize1;
3663
3664 // head1
3665 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_01_02, (u32StartAddr0 >> MIU_BUS));
3666 // end1
3667 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_05_06, (u32EndAddr0 >> MIU_BUS));
3668 // mid1
3669 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_03_04, (u32StartAddr0 >> MIU_BUS));
3670
3671 // head2
3672 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_07_08, (u32StartAddr1 >> MIU_BUS));
3673 // end2
3674 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_0B_0C, (u32EndAddr1 >> MIU_BUS));
3675 // mid2
3676 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_09_0A, (u32StartAddr1 >> MIU_BUS));
3677 }
3678
3679 #endif
3680
HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32StartAddr1)3681 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1)
3682 {
3683 if(u32PVREng >= TSP_PVRENG_NUM)
3684 {
3685 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3686 return;
3687 }
3688
3689 // Check MIU select
3690 MS_U8 u8MiuSel;
3691 MS_PHY phyMiuOffsetPvrBuf0, phyMiuOffsetPvrBuf1;
3692 MS_U8 u8Shift = u32PVREng * TSP_MIU_SEL_BITS_LEN;
3693
3694 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf0, u32StartAddr0);
3695 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf1, u32StartAddr1);
3696
3697 // Select MIU
3698 REG32_MSK_W(&_RegTopCtrl->CFG_TOP_05_06, (CFG_TOP_05_06_REG_MIU_SEL_PVR_MASK << u8Shift), (u8MiuSel << (CFG_TOP_05_06_REG_MIU_SEL_PVR_SHIFT + u8Shift)));
3699
3700 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3701 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3702
3703 // head1
3704 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_01_02, (phyMiuOffsetPvrBuf0 >> MIU_BUS));
3705 // head2
3706 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_07_08, (phyMiuOffsetPvrBuf1 >> MIU_BUS));
3707 }
3708
HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng,MS_U32 u32MidAddr0,MS_U32 u32MidAddr1)3709 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng, MS_U32 u32MidAddr0, MS_U32 u32MidAddr1)
3710 {
3711 if(u32PVREng >= TSP_PVRENG_NUM)
3712 {
3713 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3714 return;
3715 }
3716
3717 // Check MIU select
3718 MS_U8 u8MiuSel;
3719 MS_PHY phyMiuOffsetPvrBuf0, phyMiuOffsetPvrBuf1;
3720 MS_U8 u8Shift = u32PVREng * TSP_MIU_SEL_BITS_LEN;
3721
3722 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf0, u32MidAddr0);
3723 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf1, u32MidAddr1);
3724
3725 // Select MIU
3726 REG32_MSK_W(&_RegTopCtrl->CFG_TOP_05_06, (CFG_TOP_05_06_REG_MIU_SEL_PVR_MASK << u8Shift), (u8MiuSel << (CFG_TOP_05_06_REG_MIU_SEL_PVR_SHIFT + u8Shift)));
3727
3728
3729 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3730 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3731
3732 // mid1
3733 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_03_04, (phyMiuOffsetPvrBuf0 >> MIU_BUS));
3734 // mid2
3735 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_09_0A, (phyMiuOffsetPvrBuf1 >> MIU_BUS));
3736 }
3737
HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng,MS_U32 u32EndAddr0,MS_U32 u32EndAddr1)3738 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1)
3739 {
3740 if(u32PVREng >= TSP_PVRENG_NUM)
3741 {
3742 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3743 return;
3744 }
3745
3746 // Check MIU select
3747 MS_U8 u8MiuSel;
3748 MS_PHY phyMiuOffsetPvrBuf0, phyMiuOffsetPvrBuf1;
3749 MS_U8 u8Shift = u32PVREng * TSP_MIU_SEL_BITS_LEN;
3750
3751 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf0, u32EndAddr0);
3752 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf1, u32EndAddr1);
3753
3754 // Select MIU
3755 REG32_MSK_W(&_RegTopCtrl->CFG_TOP_05_06, (CFG_TOP_05_06_REG_MIU_SEL_PVR_MASK << u8Shift), (u8MiuSel << (CFG_TOP_05_06_REG_MIU_SEL_PVR_SHIFT + u8Shift)));
3756
3757
3758 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3759 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3760
3761 // end1
3762 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_05_06, (u32EndAddr0 >> MIU_BUS));
3763 // end2
3764 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_0B_0C, (u32EndAddr1 >> MIU_BUS));
3765 }
3766
HAL_PVR_GetWritePtr(MS_U32 u32PVREng)3767 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng)
3768 {
3769 if(u32PVREng >= TSP_PVRENG_NUM)
3770 {
3771 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
3772 return 0;
3773 }
3774
3775 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3776 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
3777
3778 return (REG32_R(&RegPvrCtrl[u8PvrEng].CFG_PVR_13_14) << MIU_BUS);
3779 }
3780
3781
HAL_PVR_GetEngSrc(MS_U32 u32EngDst,TSP_SRC_SEQ * eSrc)3782 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc)
3783 {
3784 if(u32EngDst >= TSP_PVRENG_NUM)
3785 {
3786 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32EngDst));
3787 return;
3788 }
3789
3790 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32EngDst < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
3791 MS_U8 u8PvrEng = (u32EngDst < E_TSP_PVR_PVRENG_8)? u32EngDst : (u32EngDst - E_TSP_PVR_PVRENG_8);
3792
3793 *eSrc = (REG16_R(&RegPvrCtrl[u8PvrEng].CFG_PVR_10) & CFG_PVR_10_REG_INPUT_SRC_MASK) >> CFG_PVR_10_REG_INPUT_SRC_SHIFT;
3794 }
3795
3796 // kaiser Only!!!
HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)3797 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)
3798 {
3799 switch (u32FileEng)
3800 {
3801 case 0: //File in Eng 0
3802 return E_FILEENG_TSIF1;
3803 case 1: //File in Eng 1
3804 return E_FILEENG_TSIF3;
3805 case 2: //File in Eng 2
3806 return E_FILEENG_TSIF0;
3807 case 3: //File in Eng 3
3808 return E_FILEENG_TSIF2;
3809 case 4:
3810 return E_FILEENG_TSIF4;
3811 case 5:
3812 return E_FILEENG_TSIF5;
3813 case 6:
3814 return E_FILEENG_TSIF6;
3815 default:
3816 return E_FILEENG_INVALID;
3817 }
3818 }
3819
3820 // @NOTE for backward competible when calling flowset pvr
3821 // kaiser Only!!!
HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)3822 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)
3823 {
3824 switch(u32Eng)
3825 {
3826 case 0:
3827 return E_TSP_SRC_PKTDMX2;
3828 case 1:
3829 return E_TSP_SRC_PKTDMX3;
3830 case 2:
3831 return E_TSP_SRC_PKTDMX2;
3832 case 3:
3833 return E_TSP_SRC_PKTDMX3;
3834 default:
3835 return E_TSP_SRC_INVALID;
3836 }
3837 }
3838
3839 // kaiser Only!!!
HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF,MS_BOOL bFileIn)3840 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF, MS_BOOL bFileIn)
3841 {
3842 MS_U32 u32PhyTSIF = 0;
3843 switch (eTSIF)
3844 {
3845 case E_TSP_HAL_TSIF_0:
3846 if(bFileIn)
3847 u32PhyTSIF = TSP_TSIF1; // @NOTE tsif1 is used for playback0 file-in
3848 else
3849 u32PhyTSIF = TSP_TSIF0;
3850 break;
3851 case E_TSP_HAL_TSIF_1:
3852 if(bFileIn)
3853 u32PhyTSIF = TSP_TSIF3; // @NOTE tsif3 is used for playback0 file-in
3854 else
3855 u32PhyTSIF = TSP_TSIF2;
3856 break;
3857 case E_TSP_HAL_TSIF_2:
3858 if(bFileIn)
3859 u32PhyTSIF = TSP_TSIF0;
3860 else
3861 u32PhyTSIF = TSP_TSIF3;
3862 break;
3863 case E_TSP_HAL_TSIF_3:
3864 if(bFileIn)
3865 u32PhyTSIF = TSP_TSIF2;
3866 else
3867 u32PhyTSIF = TSP_TSIF1;
3868 break;
3869 case E_TSP_HAL_TSIF_4:
3870 u32PhyTSIF = TSP_TSIF4;
3871 break;
3872 case E_TSP_HAL_TSIF_5:
3873 u32PhyTSIF = TSP_TSIF5;
3874 break;
3875 case E_TSP_HAL_TSIF_6:
3876 u32PhyTSIF = TSP_TSIF6;
3877 break;
3878 case E_TSP_HAL_TSIF_PVR0:
3879 u32PhyTSIF = TSP_TSIF2;
3880 break;
3881 case E_TSP_HAL_TSIF_PVR1:
3882 u32PhyTSIF = TSP_TSIF3;
3883 break;
3884 case E_TSP_HAL_TSIF_PVR2:
3885 u32PhyTSIF = TSP_TSIF2;
3886 break;
3887 case E_TSP_HAL_TSIF_PVR3:
3888 u32PhyTSIF = TSP_TSIF3;
3889 break;
3890 default:
3891 printf("[PVR ERROR][%s][%d] mapping TSIF error\n",__FUNCTION__,__LINE__);
3892 break;
3893 }
3894
3895 return u32PhyTSIF;
3896 }
3897
3898 // kaiser Only!!!
HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)3899 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)
3900 {
3901 // @NOTE we map hw pkt dmx setting to api layer flow at this function
3902
3903 TSP_PIDFLT_SRC ePidFltSrc = E_TSP_PIDFLT_INVALID;
3904
3905 switch (eSrc)
3906 {
3907 case E_TSP_SRC_PKTDMX0:
3908 ePidFltSrc = E_TSP_PIDFLT_LIVE0;
3909 break;
3910 case E_TSP_SRC_PKTDMX1:
3911 ePidFltSrc = E_TSP_PIDFLT_FILE0;
3912 break;
3913 case E_TSP_SRC_PKTDMX2:
3914 ePidFltSrc = E_TSP_PIDFLT_LIVE1;
3915 break;
3916 case E_TSP_SRC_PKTDMX3:
3917 ePidFltSrc = E_TSP_PIDFLT_FILE1;
3918 break;
3919 case E_TSP_SRC_PKTDMX4:
3920 ePidFltSrc = E_TSP_PIDFLT_LIVE4;
3921 break;
3922 case E_TSP_SRC_PKTDMX5:
3923 ePidFltSrc = E_TSP_PIDFLT_LIVE5;
3924 break;
3925 case E_TSP_SRC_PKTDMX6:
3926 ePidFltSrc = E_TSP_PIDFLT_LIVE6;
3927 break;
3928 default:
3929 // @TODO add assert
3930 printf ("[TSP_ERR][%s][%d] Wrong Engine Source!!\n", __FUNCTION__,__LINE__);
3931 break;
3932 }
3933
3934 return ePidFltSrc;
3935 }
3936
HAL_TSP_GetDefaultFileinEng(void)3937 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void)
3938 {
3939 return E_FILEENG_TSIF1;
3940 }
3941
HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType,MS_U32 u32Eng)3942 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng)
3943 {
3944 if(eDstType == E_TSP_PIDFLT_DST_VIDEO)
3945 {
3946 switch(u32Eng)
3947 {
3948 case 0:
3949 return TSP_PIDFLT_OUT_VFIFO;
3950 case 1:
3951 return TSP_PIDFLT_OUT_VFIFO3D;
3952 case 2:
3953 return TSP_PIDFLT_OUT_VFIFO3;
3954 case 3:
3955 return TSP_PIDFLT_OUT_VFIFO4;
3956 case 4:
3957 return TSP_PIDFLT_OUT_VFIFO5;
3958 case 5:
3959 return TSP_PIDFLT_OUT_VFIFO6;
3960 case 6:
3961 return TSP_PIDFLT_OUT_VFIFO7;
3962 case 7:
3963 return TSP_PIDFLT_OUT_VFIFO8;
3964 default:
3965 printf("[TSP ERROR][%s][%d] mapping Vfifo eng error\n", __FUNCTION__, __LINE__);
3966 return 0;
3967 }
3968 }
3969 else if(eDstType == E_TSP_PIDFLT_DST_AUDIO)
3970 {
3971 switch(u32Eng)
3972 {
3973 case 0:
3974 return TSP_PIDFLT_OUT_AFIFO;
3975 case 1:
3976 return TSP_PIDFLT_OUT_AFIFO2;
3977 case 2:
3978 return TSP_PIDFLT_OUT_AFIFO3;
3979 case 3:
3980 return TSP_PIDFLT_OUT_AFIFO4;
3981 case 4:
3982 return TSP_PIDFLT_OUT_AFIFO5;
3983 case 5:
3984 return TSP_PIDFLT_OUT_AFIFO6;
3985 default:
3986 printf("[TSP ERROR][%s][%d] mapping Afifo eng error\n", __FUNCTION__, __LINE__);
3987 return 0;
3988 }
3989 }
3990 else if(eDstType == E_TSP_PIDFLT_DST_PVR)
3991 {
3992 switch(u32Eng)
3993 {
3994 case 0:
3995 return TSP_PIDFLT_OUT_PVR1;
3996 case 1:
3997 return TSP_PIDFLT_OUT_PVR2;
3998 case 2:
3999 return TSP_PIDFLT_OUT_PVR3;
4000 case 3:
4001 return TSP_PIDFLT_OUT_PVR4;
4002 case 4:
4003 return TSP_PIDFLT_OUT_PVR5;
4004 case 5:
4005 return TSP_PIDFLT_OUT_PVR6;
4006 case 6:
4007 return TSP_PIDFLT_OUT_PVR7;
4008 case 7:
4009 return TSP_PIDFLT_OUT_PVR8;
4010 case 8:
4011 return TSP_PIDFLT_OUT_PVR9;
4012 case 9:
4013 return TSP_PIDFLT_OUT_PVR10;
4014
4015 default:
4016 printf("[TSP ERROR][%s][%d] mapping PVR eng error\n", __FUNCTION__, __LINE__);
4017 return 0;
4018 }
4019 }
4020 else
4021 {
4022 printf("[TSP ERROR][%s][%d] pid filter destination type error\n", __FUNCTION__, __LINE__);
4023 return 0;
4024 }
4025 }
4026
HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif)4027 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif)
4028 {
4029 MS_U32 u32Fq = 0;
4030
4031 switch (u32Tsif)
4032 {
4033 case 0:
4034 u32Fq = 0;
4035 break;
4036 case 1:
4037 u32Fq = 2;
4038 break;
4039 case 2:
4040 u32Fq = 3;
4041 break;
4042 case 3:
4043 u32Fq = 1;
4044 break;
4045 case 4 ... 10: //exclude 7
4046 u32Fq = u32Tsif;
4047 break;
4048 default:
4049 printf("[PVR ERROR][%s][%d] mapping TSIF:%u error\n",__FUNCTION__,__LINE__,(unsigned int)u32Tsif);
4050 break;
4051 }
4052
4053 return u32Fq;
4054 }
4055
HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)4056 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)
4057 {
4058 switch(u8Pad3WireId)
4059 {
4060 case 4:
4061 return E_TSP_TS_PAD_EXT4;
4062 case 5:
4063 return E_TSP_TS_PAD_EXT5;
4064 case 6:
4065 return E_TSP_TS_PAD_EXT6;
4066 case 7:
4067 return E_TSP_TS_PAD_EXT7;
4068 default:
4069 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] mapping 3WirePad:%u error\n",__FUNCTION__,__LINE__,u8Pad3WireId));
4070 return E_TSP_TS_PAD_INVALID;
4071 }
4072 }
4073
HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng,MS_BOOL bSet)4074 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng, MS_BOOL bSet)
4075 {
4076 if(u32PVREng >= TSP_PVRENG_NUM)
4077 {
4078 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
4079 return;
4080 }
4081
4082 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
4083 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
4084
4085 if(bSet)
4086 {
4087 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_PKT192_EN);
4088 }
4089 else
4090 {
4091 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_PKT192_EN);
4092 }
4093 }
4094
HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)4095 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)
4096 {
4097 MS_U32 u32lpcr = 0;
4098
4099 if(u32PVREng >= TSP_PVRENG_NUM)
4100 {
4101 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
4102 return 0;
4103 }
4104
4105 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
4106 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
4107
4108 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_LPCR1_RLD);
4109 u32lpcr = REG32_R(&RegPvrCtrl[u8PvrEng].CFG_PVR_17_18);
4110 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_LPCR1_RLD);
4111
4112 return u32lpcr;
4113 }
4114
HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng,MS_U32 u32Stamp)4115 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32Stamp)
4116 {
4117 if(u32PVREng >= TSP_PVRENG_NUM)
4118 {
4119 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
4120 return;
4121 }
4122
4123 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
4124 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
4125
4126 //reset pvr control registers
4127 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_LPCR1_WLD);
4128 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_15_16, u32Stamp);
4129 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_00, CFG_PVR_00_REG_PVR_LPCR1_WLD);
4130 }
4131
4132 /*
4133 void HAL_PVR_SetTSIF(MS_U32 u32PVREng , MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP)
4134 {
4135 if (bPara)
4136 {
4137 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
4138 }
4139 else
4140 {
4141 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
4142 }
4143
4144 if (bExtSync)
4145 {
4146 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
4147 }
4148 else
4149 {
4150 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
4151 }
4152
4153 if (bDataSWP)
4154 {
4155 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
4156 }
4157 else
4158 {
4159 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
4160 }
4161 }
4162
4163 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis)
4164 {
4165 if(bDis)
4166 {
4167 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
4168 }
4169 else
4170 {
4171 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
4172 }
4173 }
4174
4175 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn)
4176 {
4177 if(bEn)
4178 {
4179 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
4180 }
4181 else
4182 {
4183 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
4184 }
4185 }
4186 */
4187
HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)4188 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)
4189 {
4190 MS_U32 u32Data;
4191
4192 //reserved
4193 switch (u32Type)
4194 {
4195
4196 case INFO_FW_VERSION:
4197 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
4198 break;
4199 case INFO_FW_DATE:
4200 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_DATE);
4201 break;
4202 default:
4203 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
4204 break;
4205
4206 }
4207
4208 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_INFO);
4209
4210 _delay(10); // supposed TSP is able to respond in 10us
4211 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4212 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4213
4214 return u32Data;
4215 }
4216
HAL_TSP_HCMD_BufRst(MS_U32 u32Value)4217 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value)
4218 {
4219 // MS_U32 u32Data;
4220
4221 REG32_W(&_RegCtrl->MCU_Data0 , u32Value);
4222 REG32_W(&_RegCtrl->MCU_Cmd , TSP_MCU_CMD_BUFRST);
4223 _delay(10); // supposed TSP is able to respond in 10us
4224
4225 return TRUE;
4226 }
4227
HAL_TSP_HCMD_Read(MS_U32 u32Addr)4228 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr)
4229 {
4230 MS_U32 u32Data;
4231
4232 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
4233 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_READ);
4234
4235 _delay(10); // supposed TSP is able to respond in 10us
4236 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4237 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4238
4239 return u32Data;
4240 }
4241
4242
HAL_TSP_HCMD_Write(MS_U32 u32Addr,MS_U32 u32Value)4243 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value)
4244 {
4245 MS_U32 u32Data;
4246
4247 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
4248 REG32_W(&_RegCtrl->MCU_Data1, u32Value);
4249 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_WRITE);
4250
4251 _delay(10); // supposed TSP is able to respond in 10us
4252 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4253 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4254
4255 return TRUE;
4256 }
4257
4258
HAL_TSP_HCMD_Alive(void)4259 MS_BOOL HAL_TSP_HCMD_Alive(void)
4260 {
4261 MS_U32 u32Data;
4262
4263 REG32_W(&_RegCtrl->MCU_Data1, 0);
4264 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_ALIVE); //@TODO check FW HCMD
4265 _delay(10); // supposed TSP is able to respond in 10us
4266 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4267 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4268
4269 return (u32Data == TSP_MCU_DATA_ALIVE)? TRUE : FALSE;
4270 }
4271
HAL_TSP_HCMD_SET(MS_U32 mcu_cmd,MS_U32 mcu_data0,MS_U32 mcu_data1)4272 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1)
4273 {
4274 REG32_W(&_RegCtrl->MCU_Data0, mcu_data0);
4275 REG32_W(&_RegCtrl->MCU_Data1, mcu_data1);
4276 REG32_W(&_RegCtrl->MCU_Cmd, mcu_cmd);
4277 }
4278
HAL_TSP_HCMD_GET(MS_U32 * pmcu_cmd,MS_U32 * pmcu_data0,MS_U32 * pmcu_data1)4279 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1)
4280 {
4281 *pmcu_cmd = REG32_R(&_RegCtrl->MCU_Cmd);
4282 *pmcu_data0 = REG32_R(&_RegCtrl->MCU_Data0);
4283 *pmcu_data1 = REG32_R(&_RegCtrl->MCU_Data1);
4284 }
4285
HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId,MS_BOOL bDis)4286 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis)
4287 {
4288 MS_U32 u32Data = bDis ;
4289
4290 REG32_W(&_RegCtrl->MCU_Data0, FltId);
4291 REG32_W(&_RegCtrl->MCU_Data1,u32Data);
4292 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SECRDYINT_DISABLE); // @TODO add HCMD list here
4293 _delay(10); // supposed TSP is able to respond in 10us
4294 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4295
4296 return ;
4297 }
4298
HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)4299 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)
4300 {
4301 MS_U32 u32Data;
4302
4303 REG32_W(&_RegCtrl->MCU_Data0, u32Enable);
4304 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_DBG);
4305
4306 _delay(10); // supposed TSP is able to respond in 10us
4307 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4308 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4309
4310 return REG32_R(&_RegCtrl->MCU_Data1);
4311 }
4312
HAL_TSP_GetDBGStatus(MS_U16 u16Sel)4313 MS_U32 HAL_TSP_GetDBGStatus(MS_U16 u16Sel)
4314 {
4315 REG16_CLR(&_RegCtrl->DBG_SEL, TSP_DBG_SEL_MASK);
4316 REG16_SET(&_RegCtrl->DBG_SEL, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK));
4317
4318 return REG32_R(&_RegCtrl->TSP_Debug);
4319 }
4320
4321 // [ToDo...]
HAL_TSP_INT_Enable(MS_U32 u32Mask)4322 void HAL_TSP_INT_Enable(MS_U32 u32Mask)
4323 {
4324 // u32Mask [0:7] for bank 0x15 7e bit[0:7]
4325 /*
4326 6: DMA read done
4327 5: HK_INT_FORCE. (it's trigger bit is at bank 15 39 bit[15])
4328 4: STR2MI_WADR meets STR2MI_MID.
4329 3: STR2MI_WADR meets STR2MI_TAIL.
4330 2: dma_status1
4331 1: dma_status2
4332 0: dma_status3
4333 */
4334 REG16_SET(&_RegCtrl->HwInt_Stat, (TSP_HWINT_EN_MASK & u32Mask));
4335
4336 // u32Mask [8:15] for bank 0x16 6c bit[0:7]
4337 /*
4338 [5] : OTV HW interrupt
4339 [4] : all DMA write address not in the protect zone interrupt
4340 [3] : vq0~vq6 overflow interrupt
4341 [2] : aud_err
4342 [1] : vid_err
4343 [0] : reg_hk_int_force (it's trigger bit is at bank 15 44 bit[15])
4344 */
4345 REG16_SET(&_RegCtrl->HwInt2_Stat, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)));
4346
4347 // u32Mask [16:23] for bank 0x16 6f bit[0:7]
4348 /*
4349 [7] : pcr filter 7 update finish
4350 [6] : pcr filter 6 update finish
4351 [5] : pcr filter 5 update finish
4352 [4] : pcr filter 4 update finish
4353 [3] : pcr filter 3 update finish
4354 [2] : pcr filter 2 update finish
4355 [1] : pcr filter 1 update finish
4356 [0] : pcr filter 0 update finish
4357 */
4358 REG16_SET(&_RegCtrl->HwInt3_Stat, (TSP_HWINT3_EN_MASK & (u32Mask >> 16)));
4359 }
4360
4361
4362 // [ToDo...]
HAL_TSP_INT_Disable(MS_U32 u32Mask)4363 void HAL_TSP_INT_Disable(MS_U32 u32Mask)
4364 {
4365 REG16_W(&_RegCtrl->HwInt_Stat,
4366 (REG16_R(&_RegCtrl->HwInt_Stat) & ~(TSP_HWINT_EN_MASK & (u32Mask))));
4367
4368 REG16_W(&_RegCtrl->HwInt2_Stat,
4369 (REG16_R(&_RegCtrl->HwInt2_Stat) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))));
4370
4371 REG16_W(&_RegCtrl->HwInt3_Stat,
4372 (REG16_R(&_RegCtrl->HwInt3_Stat) & ~(TSP_HWINT3_EN_MASK & (u32Mask >> 16))));
4373 }
4374
4375
4376 // [ToDo...]
HAL_TSP_INT_ClrHW(MS_U32 u32Mask)4377 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask)
4378 {
4379 REG16_SET(&_RegCtrl->HwInt_Stat, ((u32Mask << TSP_HWINT_STATUS_SHIFT) & TSP_HWINT_STATUS_MASK));
4380 REG16_CLR(&_RegCtrl->HwInt_Stat, ((u32Mask << TSP_HWINT_STATUS_SHIFT) & TSP_HWINT_STATUS_MASK));
4381
4382 REG16_SET(&_RegCtrl->HwInt2_Stat, (((u32Mask >> 8) << TSP_HWINT2_STATUS_SHIFT) & TSP_HWINT2_STATUS_MASK));
4383 REG16_CLR(&_RegCtrl->HwInt2_Stat, (((u32Mask >> 8) << TSP_HWINT2_STATUS_SHIFT) & TSP_HWINT2_STATUS_MASK));
4384
4385 REG16_SET(&_RegCtrl->HwInt3_Stat, (((u32Mask >> 16) << TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATUS_MASK));
4386 REG16_CLR(&_RegCtrl->HwInt3_Stat, (((u32Mask >> 16) << TSP_HWINT3_STATUS_SHIFT) & TSP_HWINT3_STATUS_MASK));
4387 }
4388
4389 // [ToDo...]
HAL_TSP_INT_GetHW(void)4390 MS_U32 HAL_TSP_INT_GetHW(void)
4391 {
4392 MS_U32 status;
4393
4394 status = (MS_U32)(((REG16_R(&_RegCtrl->HwInt3_Stat) & TSP_HWINT3_STATUS_MASK) >> TSP_HWINT3_STATUS_SHIFT) << 16);
4395
4396
4397 status |= ((MS_U32)(((REG16_R(&_RegCtrl->HwInt2_Stat) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STATUS_SHIFT) << 8));
4398
4399
4400 status |= ((MS_U32)((REG16_R(&_RegCtrl->HwInt_Stat) & TSP_HWINT_STATUS_MASK) >> TSP_HWINT_STATUS_SHIFT));
4401
4402 return (status & 0x00FFFFFF);
4403 }
4404
HAL_TSP_INT_ClrSW(void)4405 void HAL_TSP_INT_ClrSW(void)
4406 {
4407 REG32_W(&_RegCtrl->SwInt_Stat, 0);
4408 }
4409
HAL_TSP_INT_GetSW(void)4410 MS_U32 HAL_TSP_INT_GetSW(void)
4411 {
4412 return REG32_R(&_RegCtrl->SwInt_Stat);
4413 }
4414
4415 #if FPGA_TEST
4416
HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx,MS_U32 inputSrc)4417 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc)
4418 {
4419 //@NOTE: K7U don't have to implement (deleted...)
4420 }
4421
HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)4422 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)
4423 {
4424 MS_U8 u8FileEng;
4425
4426 if(bByPassEn)
4427 {
4428 for(u8FileEng = 0; u8FileEng < E_FILEENG_TSIF4; u8FileEng++)
4429 {
4430 REG16_SET(&_RegFile0Ctrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_SPD_TSIF_BYPASS);
4431 }
4432
4433 for(u8FileEng = 0; u8FileEng <= (E_FILEENG_TSIF6 - E_FILEENG_TSIF4); u8FileEng++)
4434 {
4435 REG16_SET(&_RegFile1Ctrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_SPD_TSIF_BYPASS);
4436 }
4437 }
4438 else
4439 {
4440 for(u8FileEng = 0; u8FileEng < E_FILEENG_TSIF4; u8FileEng++)
4441 {
4442 REG16_CLR(&_RegFile0Ctrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_SPD_TSIF_BYPASS);
4443 }
4444
4445 for(u8FileEng = 0; u8FileEng <= (E_FILEENG_TSIF6 - E_FILEENG_TSIF4); u8FileEng++)
4446 {
4447 REG16_CLR(&_RegFile1Ctrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_SPD_TSIF_BYPASS);
4448 }
4449 }
4450 }
4451
HAL_TSP_FileIn_SPDConfig(MS_U32 tsIf,MS_BOOL CTR_mode)4452 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsIf, MS_BOOL CTR_mode)
4453 {
4454 if(tsIf >= TSP_TSIF_NUM)
4455 {
4456 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,tsIf));
4457 return;
4458 }
4459
4460 if(CTR_mode)
4461 {
4462 REG16_SET(&_RegSpdCtrl[tsIf].CFG_SPD_05, CFG_SPD_05_REG_CTR_MODE_SPD_FILEIN); //set CTR mode enable
4463 REG16_W(&_RegSpdCtrl[tsIf].CFG_SPD_00_03[0], 0x0000); //set counter IV
4464 REG16_W(&_RegSpdCtrl[tsIf].CFG_SPD_00_03[1], 0x0000);
4465 REG16_W(&_RegSpdCtrl[tsIf].CFG_SPD_00_03[2], 0x0000);
4466 REG16_W(&_RegSpdCtrl[tsIf].CFG_SPD_00_03[3], 0x0000);
4467 REG16_W(&_RegSpdCtrl[tsIf].CFG_SPD_04, CFG_SPD_04_CTR_IV_SPD_MAX_1K); //set counter IV max vld
4468 REG16_SET(&_RegSpdCtrl[tsIf].CFG_SPD_05, CFG_SPD_05_REG_LOAD_INIT_COUNTER_SPD); //load counter IV
4469 }
4470 else
4471 {
4472 REG16_CLR(&_RegSpdCtrl[tsIf].CFG_SPD_05, CFG_SPD_05_REG_CTR_MODE_SPD_FILEIN);
4473 }
4474
4475 REG16_MSK_W(&_RegOtherCtrl->CFG_OTHER_1F, CFG_OTHER_1F_REG_SRC_AES_FILEIN_KEY_MASK, (tsIf << CFG_OTHER_1F_REG_SRC_AES_FILEIN_KEY_SHIFT));
4476 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[0], 0x0000); //file-in SPD key
4477 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[1], 0x0000);
4478 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[2], 0x0000);
4479 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[3], 0x0000);
4480 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[4], 0x1111);
4481 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[5], 0x1111);
4482 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[6], 0x1111);
4483 REG16_W(&_RegOtherCtrl->CFG_OTHER_28_2F[7], 0x1111);
4484
4485 REG_FILE_ENG_Ctrl *RegFileCtrl = (tsIf < E_FILEENG_TSIF4)? _RegFile0Ctrl : _RegFile1Ctrl;
4486 MS_U8 u8FileEng = (tsIf < E_FILEENG_TSIF4)? tsIf : (tsIf - E_FILEENG_TSIF4);
4487
4488 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_LOAD_SPD_KEY);
4489 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_SPD_TSIF_BYPASS);
4490 REG16_SET(&RegFileCtrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_TSIF_SPD_RST);
4491 REG16_CLR(&RegFileCtrl[u8FileEng].CFG_FILE_0F, CFG_FILE_0F_REG_TSIF_SPD_RST);
4492 }
4493
4494 #endif
4495
HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap,MS_U32 * pu32CapInfo)4496 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo)
4497 {
4498 switch (eCap)
4499 {
4500 case E_TSP_HAL_CAP_TYPE_PIDFLT_NUM :
4501 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PIDFLT_NUM;
4502 break;
4503
4504 case E_TSP_HAL_CAP_TYPE_SECFLT_NUM :
4505 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECFLT_NUM;
4506 break;
4507
4508 case E_TSP_HAL_CAP_TYPE_SECBUF_NUM :
4509 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_NUM;
4510 break;
4511
4512 case E_TSP_HAL_CAP_TYPE_RECENG_NUM :
4513 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECENG_NUM;
4514 break;
4515
4516 case E_TSP_HAL_CAP_TYPE_RECFLT_NUM :
4517 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_NUM;
4518 break;
4519
4520 case E_TSP_HAL_CAP_TYPE_TSIF_NUM :
4521 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSIF_NUM;
4522 break;
4523
4524 case E_TSP_HAL_CAP_TYPE_DEMOD_NUM :
4525 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_DEMOD_NUM;
4526 break;
4527
4528 case E_TSP_HAL_CAP_TYPE_TSPAD_NUM :
4529 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSPAD_NUM;
4530 break;
4531
4532 case E_TSP_HAL_CAP_TYPE_VQ_NUM :
4533 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_NUM;
4534 break;
4535
4536 case E_TSP_HAL_CAP_TYPE_CAFLT_NUM :
4537 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAFLT_NUM;
4538 break;
4539
4540 case E_TSP_HAL_CAP_TYPE_CAKEY_NUM :
4541 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAKEY_NUM;
4542 break;
4543
4544 case E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN :
4545 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_ALIGN;
4546 break;
4547
4548 case E_TSP_HAL_CAP_TYPE_PVR_ALIGN:
4549 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PVR_ALIGN;
4550 break;
4551
4552 case E_TSP_HAL_CAP_TYPE_FW_ALIGN :
4553 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_ALIGN;
4554 break;
4555
4556 case E_TSP_HAL_CAP_TYPE_VQ_ALIGN :
4557 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_ALIGN;
4558 break;
4559
4560 case E_TSP_HAL_CAP_TYPE_VQ_PITCH :
4561 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_PITCH;
4562 break;
4563
4564 case E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM:
4565 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM;
4566 break;
4567
4568 case E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM:
4569 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM;
4570 break;
4571
4572 case E_TSP_HAL_CAP_TYPE_HW_TYPE:
4573 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HW_TYPE;
4574 break;
4575
4576 case E_TSP_HAL_CAP_TYPE_RECFLT_IDX :
4577 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_IDX;
4578 break;
4579
4580 case E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX :
4581 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX;
4582 break;
4583
4584 case E_TSP_HAL_CAP_TYPE_VFIFO_NUM:
4585 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VFIFO_NUM;
4586 break;
4587
4588 case E_TSP_HAL_CAP_TYPE_AFIFO_NUM:
4589 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_AFIFO_NUM;
4590 break;
4591
4592 case E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT:
4593 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT;
4594 break;
4595
4596 case E_TSP_HAL_CAP_FIQ_NUM:
4597 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FIQ_NUM;
4598 break;
4599
4600 case E_TSP_HAL_CAP_FW_BUF_SIZE:
4601 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_BUF_SIZE;
4602 break;
4603 case E_TSP_HAL_CAP_FW_BUF_RANGE:
4604 *(pu32CapInfo) = TSP_FW_BUF_LOW_BUD;
4605 *(pu32CapInfo + 1) = TSP_FW_BUF_UP_BUD;
4606 break;
4607 case E_TSP_HAL_CAP_VQ_BUF_RANGE:
4608 *(pu32CapInfo) = TSP_VQ_BUF_LOW_BUD;
4609 *(pu32CapInfo + 1) = TSP_VQ_BUF_UP_BUD;
4610 break;
4611 case E_TSP_HAL_CAP_SEC_BUF_RANGE:
4612 *(pu32CapInfo) = TSP_SEC_BUF_LOW_BUD;
4613 *(pu32CapInfo + 1) = TSP_SEC_BUF_UP_BUD;
4614 break;
4615 default:
4616 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_NULL;
4617 return FALSE;
4618 }
4619
4620 return TRUE;
4621 }
4622
HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)4623 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)
4624 {
4625 MS_U8 u8Idx = 0;
4626
4627 if(bEnable)
4628 {
4629 for(u8Idx = 0; u8Idx < E_TSP_HAL_CAP_VAL_AFIFO_NUM; u8Idx++)
4630 {
4631 REG16_SET(&_RegAudioCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_DUP_PKT_SKIP);
4632 }
4633
4634 for(u8Idx = 0; u8Idx < E_TSP_HAL_CAP_VAL_VFIFO_NUM; u8Idx++)
4635 {
4636 REG16_SET(&_RegVideoCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_DUP_PKT_SKIP);
4637 }
4638 }
4639 else
4640 {
4641 for(u8Idx = 0; u8Idx < E_TSP_HAL_CAP_VAL_AFIFO_NUM; u8Idx++)
4642 {
4643 REG16_CLR(&_RegAudioCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_DUP_PKT_SKIP);
4644 }
4645
4646 for(u8Idx = 0; u8Idx < E_TSP_HAL_CAP_VAL_VFIFO_NUM; u8Idx++)
4647 {
4648 REG16_CLR(&_RegVideoCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_DUP_PKT_SKIP);
4649 }
4650 }
4651 }
4652
HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType,MS_BOOL bEnable)4653 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable)
4654 {
4655 if(eHalPktType <= E_TSP_HAL_TEI_REMOVE_AUDIO6_PKT)
4656 {
4657 MS_U8 u8AudioFltIdx = eHalPktType - E_TSP_HAL_TEI_REMOVE_AUDIO_PKT;
4658
4659 if(bEnable)
4660 {
4661 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PES_ERR_RM_EN);
4662 }
4663 else
4664 {
4665 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PES_ERR_RM_EN);
4666 }
4667 }
4668 else if((eHalPktType >= E_TSP_HAL_TEI_REMOVE_VIDEO_PKT) && (eHalPktType <= E_TSP_HAL_TEI_REMOVE_VIDEO8_PKT))
4669 {
4670 MS_U8 u8VideoFltIdx = eHalPktType - E_TSP_HAL_TEI_REMOVE_VIDEO_PKT;
4671
4672 if(bEnable)
4673 {
4674 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PES_ERR_RM_EN);
4675 }
4676 else
4677 {
4678 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PES_ERR_RM_EN);
4679 }
4680 }
4681 else
4682 {
4683 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
4684 }
4685 }
4686
4687 #if FPGA_TEST
4688
HAL_TSP_TEI_SKIP(MS_U32 tsIf,MS_BOOL bEnable)4689 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable)
4690 {
4691 if(tsIf >= TSP_TSIF_NUM)
4692 {
4693 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,tsIf));
4694 return;
4695 }
4696
4697 if(bEnable)
4698 {
4699 REG16_SET(&_RegPathCtrl[tsIf].CFG_PATH_08, CFG_PATH_08_REG_TEI_SKIP_PKT);
4700 }
4701 else
4702 {
4703 REG16_CLR(&_RegPathCtrl[tsIf].CFG_PATH_08, CFG_PATH_08_REG_TEI_SKIP_PKT);
4704 }
4705 }
4706
4707 #endif
4708
HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)4709 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)
4710 {
4711 if(bEn == TRUE)
4712 {
4713 REG16_SET(&_RegCtrl->reg160C, TSP_ORZ_DMAW_PROT_EN);
4714 }
4715 else
4716 {
4717 REG16_CLR(&_RegCtrl->reg160C, TSP_ORZ_DMAW_PROT_EN);
4718 }
4719 }
4720
HAL_TSP_OR_Address_Protect(MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)4721 void HAL_TSP_OR_Address_Protect(MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
4722 {
4723 MS_U8 u8MiuSel;
4724 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
4725
4726 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
4727 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
4728
4729 if(u8MiuSel < E_CHIP_MIU_NUM)
4730 {
4731 REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK));
4732 REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK));
4733 }
4734 }
4735
HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)4736 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)
4737 {
4738 if(bEn == TRUE)
4739 {
4740 REG16_SET(&_RegCtrl->reg15b4, TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
4741 }
4742 else
4743 {
4744 REG16_CLR(&_RegCtrl->reg15b4, TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
4745 }
4746 }
4747
HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID,MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)4748 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
4749 {
4750 MS_U8 u8MiuSel;
4751 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
4752
4753 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
4754 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
4755
4756 if(u8MiuSel < E_CHIP_MIU_NUM)
4757 {
4758 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_DMAW_BND_MASK);
4759 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_DMAW_BND_MASK);
4760
4761 switch(u8SecID)
4762 {
4763 case 0:
4764 REG32_W(&_RegCtrl->DMAW_LBND0, u32LBnd);
4765 REG32_W(&_RegCtrl->DMAW_UBND0, u32UBnd);
4766 break;
4767 case 1:
4768 REG32_W(&_RegCtrl->DMAW_LBND1, u32LBnd);
4769 REG32_W(&_RegCtrl->DMAW_UBND1, u32UBnd);
4770 break;
4771 default:
4772 break;
4773 }
4774 }
4775 }
4776
HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable)4777 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng, MS_BOOL bEnable)
4778 {
4779 if(u32PVREng >= TSP_PVRENG_NUM)
4780 {
4781 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
4782 return;
4783 }
4784
4785 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
4786 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
4787
4788 if(bEnable)
4789 {
4790 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_PVR_DMAW_PROTECT_EN);
4791 }
4792 else
4793 {
4794 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_0D, CFG_PVR_0D_REG_PVR_DMAW_PROTECT_EN);
4795 }
4796 }
4797
HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng,MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)4798 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng, MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
4799 {
4800 if(u32PVREng >= TSP_PVRENG_NUM)
4801 {
4802 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
4803 return;
4804 }
4805
4806 MS_U8 u8MiuSel;
4807 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
4808
4809 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
4810 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
4811
4812 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32PVREng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
4813 MS_U8 u8PvrEng = (u32PVREng < E_TSP_PVR_PVRENG_8)? u32PVREng : (u32PVREng - E_TSP_PVR_PVRENG_8);
4814
4815 if(u8MiuSel < E_CHIP_MIU_NUM)
4816 {
4817 MS_U32 u32LBnd = (MS_U32)(phyMiuOffsetLB >> MIU_BUS);
4818 MS_U32 u32UBnd = (MS_U32)(phyMiuOffsetUB >> MIU_BUS);
4819
4820 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_1C_1D, u32LBnd);
4821 REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_1E_1F, u32UBnd);
4822 }
4823 }
4824
HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)4825 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)
4826 {
4827 if(u32MMFIEng >= 2)
4828 {
4829 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong MMFI Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32MMFIEng));
4830 return;
4831 }
4832
4833 if(bEnable)
4834 {
4835 REG16_SET(&_RegOtherCtrl->CFG_OTHER_18, (CFG_OTHER_18_REG_MMFI0_DMAR_PROTECT_EN << u32MMFIEng));
4836 }
4837 else
4838 {
4839 REG16_CLR(&_RegOtherCtrl->CFG_OTHER_18, (CFG_OTHER_18_REG_MMFI0_DMAR_PROTECT_EN << u32MMFIEng));
4840 }
4841 }
4842
HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32UpBoundAddr,MS_PHY u32LowBoundAddr)4843 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng, MS_PHY u32UpBoundAddr, MS_PHY u32LowBoundAddr)
4844 {
4845 if(u32MMFIEng >= 2)
4846 {
4847 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong MMFI Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32MMFIEng));
4848 return;
4849 }
4850
4851 MS_U8 u8MiuSel;
4852 MS_PHY phyMiuOffsetLB, phyMiuOffsetUB;
4853
4854 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetLB, u32LowBoundAddr);
4855 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetUB, u32UpBoundAddr);
4856
4857 if(u8MiuSel < E_CHIP_MIU_NUM)
4858 {
4859 MS_U32 u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK);
4860 MS_U32 u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK);
4861
4862 REG32_W(&_RegTopCtrl->CFG_TOP_50_57[u32MMFIEng].L_BND, u32LBnd);
4863 REG32_W(&_RegTopCtrl->CFG_TOP_50_57[u32MMFIEng].U_BND, u32UBnd);
4864 }
4865 }
4866
HAL_TSP_SaveFltState(void)4867 void HAL_TSP_SaveFltState(void)
4868 {
4869 MS_U32 u32Size;
4870 TSP32 * pRegEnd;
4871 TSP32 * pReg;
4872 int i, j;
4873
4874 for (i = 0; i < TSP_PIDFLT_NUM; i++)
4875 {
4876 _u32PidFltReg[i] = TSP32_IdrR(&(_REGPid0->Flt[i]));
4877 _u32PidDstReg[i] = TSP32_IdrR(&(_REGPid1->Flt[i]));
4878 _u32PidDst2Reg[i] = TSP32_IdrR(&(_REGPid2->Flt[i]));
4879 }
4880
4881 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x54))/sizeof(TSP32);
4882 for (i = 0; i < TSP_SECFLT_NUM; i++)
4883 {
4884 pReg = (TSP32*)&(_REGSec->Flt[i]);
4885 pRegEnd = pReg + u32Size;
4886 j = 0;
4887 for ( ; pReg < pRegEnd; pReg++)
4888 {
4889 _u32SecReg[i*u32Size+j] = TSP32_IdrR(pReg);
4890 j++;
4891 }
4892 }
4893 }
4894
HAL_TSP_CMD_Run(MS_U32 u32Cmd,MS_U32 u32Config0,MS_U32 u32Config1,MS_U32 * pData)4895 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData)
4896 {
4897 MS_U32 u32Data = 0;
4898 MS_BOOL brtn = FALSE;
4899 //printf("\033[31m [%s] Mode = %lX , Config0 =%lX , Config1 = %lX \033[m\n",__FUNCTION__,u32Cmd,u32Config0,u32Config1); // Eason test
4900 switch (u32Cmd)
4901 {
4902 case HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK:
4903 REG32_W(&_RegCtrl->MCU_Data1, u32Config0);
4904 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SEC_CC_CHECK_DISABLE);
4905 _delay(10); // supposed TSP is able to respond in 10us
4906 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
4907 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
4908 brtn = (u32Data == TSP_MCU_CMD_SEC_CC_CHECK_DISABLE)? TRUE : FALSE;
4909 break;
4910 default:
4911 break;
4912 }
4913 return brtn;
4914 }
4915
HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng,MS_U16 u16CaPvrMode,MS_BOOL bEnable)4916 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable)
4917 {
4918 if(u32Eng >= TSP_PVRENG_NUM)
4919 {
4920 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32Eng));
4921 return FALSE;
4922 }
4923
4924 REG_PVR_ENG_Ctrl *RegPvrCtrl = (u32Eng < E_TSP_PVR_PVRENG_8)? _RegPvrCtrl : _RegPvrCtrl_1;
4925 MS_U8 u8PvrEng = (u32Eng < E_TSP_PVR_PVRENG_8)? u32Eng : (u32Eng - E_TSP_PVR_PVRENG_8);
4926
4927 if(bEnable)
4928 {
4929 if(u16CaPvrMode != 0)
4930 {
4931 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_10, CFG_PVR_10_REG_REC_CA_UPPER_PATH);
4932 }
4933
4934 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_1B, CFG_PVR_1B_REG_PKT_192_SPS_EN);
4935 }
4936 else
4937 {
4938 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_10, CFG_PVR_10_REG_REC_CA_UPPER_PATH);
4939 REG16_CLR(&RegPvrCtrl[u8PvrEng].CFG_PVR_1B, CFG_PVR_1B_REG_PKT_192_SPS_EN);
4940 }
4941
4942 return TRUE;
4943 }
4944
4945 //@TODO
4946 #if FPGA_TEST
4947
HAL_TSP_PVR_SPSConfig(MS_U32 u32PVREng,MS_BOOL CTR_mode)4948 void HAL_TSP_PVR_SPSConfig(MS_U32 u32PVREng, MS_BOOL CTR_mode)
4949 {
4950 if(u32PVREng >= TSP_PVRENG_NUM)
4951 {
4952 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PVR Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32PVREng));
4953 return;
4954 }
4955
4956 REG_PVR_ENG_Ctrl *RegPvrCtrl = NULL;
4957 REG_SPS_ENG_Ctrl *RegSpsCtrl = NULL;
4958 MS_U8 u8PvrEng = 0;
4959
4960 if(u32PVREng < E_TSP_PVR_PVRENG_8)
4961 {
4962 u8PvrEng = u32PVREng;
4963 RegPvrCtrl = _RegPvrCtrl;
4964 RegSpsCtrl = _RegSpsCtrl;
4965 }
4966 else
4967 {
4968 u8PvrEng = u32PVREng - E_TSP_PVR_PVRENG_8;
4969 RegPvrCtrl = _RegPvrCtrl_1;
4970 RegSpsCtrl = _RegSpsCtrl_1;
4971 }
4972
4973 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_1B, CFG_PVR_1B_REG_PKT_192_SPS_EN);
4974 REG16_MSK_W(&_RegOtherCtrl->CFG_OTHER_1F, CFG_OTHER_1F_REG_SRC_AES_PVR_KEY_MASK, ((MS_U16)u32PVREng << CFG_OTHER_1F_REG_SRC_AES_PVR_KEY_SHIFT));
4975 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[0], 0x0000);
4976 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[1], 0x0000);
4977 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[2], 0x0000);
4978 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[3], 0x0000);
4979 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[4], 0x1111);
4980 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[5], 0x1111);
4981 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[6], 0x1111);
4982 REG16_W(&_RegOtherCtrl->CFG_OTHER_20_27[7], 0x1111);
4983 REG16_SET(&RegPvrCtrl[u8PvrEng].CFG_PVR_1B, CFG_PVR_1B_REG_LOAD_SPS_KEY);
4984
4985 if(CTR_mode)
4986 {
4987 REG16_SET(&RegSpsCtrl[u8PvrEng].CFG_SPS_05, CFG_SPS_05_REG_CTR_MODE_SPS_PVR); //set CTR mode
4988 REG16_W(&RegSpsCtrl[u8PvrEng].CFG_SPS_00_03[0], 0x0000); //set counter IV
4989 REG16_W(&RegSpsCtrl[u8PvrEng].CFG_SPS_00_03[1], 0x0000);
4990 REG16_W(&RegSpsCtrl[u8PvrEng].CFG_SPS_00_03[2], 0x0000);
4991 REG16_W(&RegSpsCtrl[u8PvrEng].CFG_SPS_00_03[3], 0x0000);
4992 REG16_W(&RegSpsCtrl[u8PvrEng].CFG_SPS_04, CFG_SPS_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld
4993 REG16_SET(&RegSpsCtrl[u8PvrEng].CFG_SPS_05, CFG_SPS_05_REG_LOAD_INIT_COUNTER_SPS); //load counter IV
4994 }
4995 else
4996 {
4997 REG16_CLR(&RegSpsCtrl[u8PvrEng].CFG_SPS_05, CFG_SPS_05_REG_CTR_MODE_SPS_PVR);
4998 }
4999 }
5000
5001 #endif
5002
5003 // u32GroupId: 0 -> filter0 ~ filter31
5004 // u32GroupId: 1 -> filter32 ~ filter63
5005 // u32GroupId: 2 -> filter64 ~ filter95
5006 // u32GroupId: 3 -> filter96 ~ filter127
5007 // u32GroupId: 4 -> filter128 ~ filter159
5008 // u32GroupId: 5 -> filter160 ~ filter191
HAL_DSCMB_GetStatus(MS_U32 u32PktDmx,MS_U32 u32GroupId,MS_U32 u32PidFltId,MS_U32 * pu32ScmbSts)5009 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts)
5010 {
5011 MS_U16 u16PktDmxSrc;
5012 MS_U16 u16WordId;
5013 MS_U32 u32PIDFltMask = u32PidFltId;
5014
5015 if(u32PidFltId != 0xFFFFFFFF)
5016 {
5017 u32PIDFltMask = (1 << (u32PidFltId & 0x1F));
5018 }
5019
5020 u16PktDmxSrc = _CLR_(REG16_R(&_RegCtrl->reg15b8), TSP_MATCH_PID_SRC_MASK);
5021
5022 switch(u32PktDmx)
5023 {
5024 case 0:
5025 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX0 << TSP_MATCH_PID_SRC_SHIFT);
5026 break;
5027 case 1:
5028 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX1 << TSP_MATCH_PID_SRC_SHIFT);
5029 break;
5030 case 2:
5031 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX2 << TSP_MATCH_PID_SRC_SHIFT);
5032 break;
5033 case 3:
5034 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX3 << TSP_MATCH_PID_SRC_SHIFT);
5035 break;
5036 case 4:
5037 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX4 << TSP_MATCH_PID_SRC_SHIFT);
5038 break;
5039 case 5:
5040 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX5 << TSP_MATCH_PID_SRC_SHIFT);
5041 break;
5042 case 6:
5043 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX6 << TSP_MATCH_PID_SRC_SHIFT);
5044 break;
5045 default:
5046 break;
5047 }
5048
5049 REG16_W(&_RegCtrl->reg15b8, u16PktDmxSrc);
5050
5051 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // Set 1 to load match_pid_num
5052
5053 // get status
5054 REG16_W(&_RegCtrl->PVRConfig, _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // freeze
5055
5056 u16WordId = _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_SEL_MASK);
5057
5058 if (u32GroupId < 24)
5059 {
5060 u16WordId = _SET_(u16WordId, u32GroupId << TSP_MATCH_PID_SEL_SHIFT);
5061 REG16_MSK_W(&_RegCtrl->PVRConfig,TSP_MATCH_PID_SEL_MASK, u16WordId);
5062 }
5063 else
5064 {
5065 printf("[TSP_ERR][%s][%d] Unsupported u32GroupId (%lu)!!!\n",__FUNCTION__, __LINE__, (long unsigned int)u32GroupId);
5066 }
5067
5068 *pu32ScmbSts = _AND_(REG32_R(&_RegCtrl->TsPidScmbStatTsin), u32PIDFltMask);
5069
5070 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // re-enable
5071
5072 if(u32PIDFltMask != 0xFFFFFFFF)
5073 {
5074 *pu32ScmbSts = ((*pu32ScmbSts > 0) ? 1: 0);
5075 }
5076
5077 return TRUE;
5078 }
5079
5080 // -------------------------------------------------------------
5081 // Merge Stream
5082 // -------------------------------------------------------------
HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path,MS_U8 u8Idx,MS_U8 * pu8SyncByte,MS_BOOL bSet)5083 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet)
5084 {
5085 if(u8Path >= TSP_TSIF_NUM)
5086 {
5087 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u8Path));
5088 return FALSE;
5089 }
5090
5091 REG16 *SynCReg = (u8Path < TSP_TSIF4)?
5092 &_RegTspMultiSyncCtrl->CFG_TSP_MULTI_SYNC_00_7F[u8Path].reg_sync_byte[u8Idx >> 1]
5093 :&_RegTspMultiSyncCtrl_1->CFG_TSP_MULTI_SYNC_00_7F[(u8Path - TSP_TSIF4)].reg_sync_byte[u8Idx >> 1];
5094 MS_U16 u16Mask = (u8Idx & 0x1)? CFG_TSP_MULTI_SYNC_BYTE_ODD_MASK : CFG_TSP_MULTI_SYNC_BYTE_EVEN_MASK;
5095 MS_U16 u16Shift = (u8Idx & 0x1)? CFG_TSP_MULTI_SYNC_BYTE_ODD_SHIFT : CFG_TSP_MULTI_SYNC_BYTE_EVEN_SHIFT;
5096
5097 if(bSet)
5098 {
5099 REG16_MSK_W(SynCReg, u16Mask, (*pu8SyncByte << u16Shift));
5100 }
5101 else
5102 {
5103 *pu8SyncByte = (MS_U8)((REG16_R(SynCReg) & u16Mask) >> u16Shift);
5104 }
5105
5106 return TRUE;
5107 }
5108
HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path,MS_U8 u8Idx,MS_U8 * pu8SrcId,MS_BOOL bSet)5109 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet)
5110 {
5111 if(u8Path >= TSP_TSIF_NUM)
5112 {
5113 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u8Path));
5114 return FALSE;
5115 }
5116
5117 REG16 *SrcIdReg = (u8Path < TSP_TSIF4)?
5118 &_RegTspMultiSyncCtrl->CFG_TSP_MULTI_SYNC_00_7F[u8Path].reg_source_id[u8Idx >> 1]
5119 :&_RegTspMultiSyncCtrl_1->CFG_TSP_MULTI_SYNC_00_7F[(u8Path - TSP_TSIF4)].reg_source_id[u8Idx >> 1];
5120 MS_U16 u16Mask = (u8Idx & 0x1)? CFG_TSP_MULTI_SRC_ID_ODD_MASK : CFG_TSP_MULTI_SRC_ID_EVEN_MASK;
5121 MS_U16 u16Shift = (u8Idx & 0x1)? CFG_TSP_MULTI_SRC_ID_ODD_SHIFT : CFG_TSP_MULTI_SRC_ID_EVEN_SHIFT;
5122
5123 if(bSet)
5124 {
5125 REG16_MSK_W(SrcIdReg, u16Mask, (*pu8SrcId << u16Shift));
5126 REG16_SET(SrcIdReg, (CFG_TSP_MULTI_SRC_ID_MULTI_SYNC_BYTE_EN << u16Shift)); // enable bit
5127 }
5128 else
5129 {
5130 *pu8SrcId = (MS_U8)((REG16_R(SrcIdReg) & u16Mask) >> u16Shift);
5131 }
5132
5133 return TRUE;
5134 }
5135
HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path,MS_U8 u8PktHeaderLen)5136 static void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen)
5137 {
5138 if(u8Path >= TSP_TSIF_NUM)
5139 {
5140 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u8Path));
5141 return;
5142 }
5143
5144 REG16 *PktConverterReg = &_RegPathCtrl[u8Path].CFG_PATH_05;
5145 REG16_MSK_W(PktConverterReg, CFG_PATH_05_MXL_PKT_HEADER_MASK, (u8PktHeaderLen << CFG_PATH_05_MXL_PKT_HEADER_SHIFT));
5146 }
5147
HAL_TSP_PktConverter_SetSyncBytePosition(MS_U8 u8Path,MS_U8 u8SyncBytePos)5148 static void HAL_TSP_PktConverter_SetSyncBytePosition(MS_U8 u8Path, MS_U8 u8SyncBytePos)
5149 {
5150 if(u8Path >= TSP_TSIF_NUM)
5151 {
5152 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u8Path));
5153 return;
5154 }
5155
5156 REG16 *PktConverterReg = &_RegPathCtrl[u8Path].CFG_PATH_05;
5157 REG16_MSK_W(PktConverterReg, CFG_PATH_05_SYNC_BYTE_POSITION_MASK, (u8SyncBytePos << CFG_PATH_05_SYNC_BYTE_POSITION_SHIFT));
5158 }
5159
HAL_TSP_PktConverter_PktMode(MS_U8 u8Path,TSP_HAL_PKT_MODE ePktMode)5160 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode)
5161 {
5162 if(u8Path >= TSP_TSIF_NUM)
5163 {
5164 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u8Path));
5165 return FALSE;
5166 }
5167
5168 REG16 *PktConverterReg = &_RegPathCtrl[u8Path].CFG_PATH_05;
5169
5170 switch(ePktMode)
5171 {
5172 case E_TSP_HAL_PKT_MODE_NORMAL:
5173 REG16_MSK_W(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_MODE_MASK, CFG_PATH_05_PKT_CONVERTER_NORMAL_MODE);
5174 break;
5175 case E_TSP_HAL_PKT_MODE_CI:
5176 REG16_MSK_W(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_MODE_MASK, CFG_PATH_05_PKT_CONVERTER_CIPLUS_MODE);
5177 break;
5178 case E_TSP_HAL_PKT_MODE_OPEN_CABLE:
5179 REG16_MSK_W(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_MODE_MASK, CFG_PATH_05_PKT_CONVERTER_OPENCABLE_MODE);
5180 break;
5181 case E_TSP_HAL_PKT_MODE_ATS:
5182 REG16_MSK_W(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_MODE_MASK, CFG_PATH_05_PKT_CONVERTER_ATS_MODE);
5183 break;
5184 case E_TSP_HAL_PKT_MODE_MXL_192:
5185 REG16_MSK_W(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_MODE_MASK, CFG_PATH_05_PKT_CONVERTER_MXL_MODE);
5186 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,4);
5187 break;
5188 case E_TSP_HAL_PKT_MODE_MXL_196:
5189 REG16_MSK_W(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_MODE_MASK, CFG_PATH_05_PKT_CONVERTER_MXL_MODE);
5190 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,8);
5191 break;
5192 case E_TSP_HAL_PKT_MODE_MXL_200:
5193 REG16_MSK_W(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_MODE_MASK, CFG_PATH_05_PKT_CONVERTER_MXL_MODE);
5194 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,12);
5195 break;
5196 case E_TSP_HAL_PKT_MODE_ND:
5197 REG16_MSK_W(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_MODE_MASK, CFG_PATH_05_PKT_CONVERTER_ND_MODE);
5198 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,1);
5199 HAL_TSP_PktConverter_SetSyncBytePosition(u8Path, 1);
5200 break;
5201 default:
5202 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong PktConverter Packet Mode!!!\n",__FUNCTION__,__LINE__));
5203 return FALSE;
5204 }
5205
5206 return TRUE;
5207 }
5208
HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path,MS_BOOL bEnable)5209 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable)
5210 {
5211 if(u8Path >= TSP_TSIF_NUM)
5212 {
5213 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u8Path));
5214 return;
5215 }
5216
5217 REG16 *PktConverterReg = &_RegPathCtrl[u8Path].CFG_PATH_05;
5218
5219 if(bEnable)
5220 {
5221 REG16_SET(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_FORCE_SYNCBYTE); // Set 1 to force sync byte be 0x47
5222 }
5223 else
5224 {
5225 REG16_CLR(PktConverterReg, CFG_PATH_05_PKT_CONVERTER_FORCE_SYNCBYTE);
5226 }
5227 }
5228
HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)5229 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)
5230 {
5231 MS_U8 u8Id;
5232 MS_U8 u8SyncByte;
5233
5234 u8SyncByte = 0x47;
5235 for(u8Id = 0; u8Id < TSP_MERGESTREAM_NUM; u8Id++,u8SyncByte++)
5236 {
5237 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Id, &u8SyncByte, TRUE);
5238 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Id, &u8Id, TRUE);
5239 }
5240 HAL_TSP_PktConverter_PktMode(u8Path,E_TSP_HAL_PKT_MODE_NORMAL);
5241 }
5242
HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path,MS_BOOL bEnable)5243 void HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path, MS_BOOL bEnable)
5244 {
5245 if(u8Path >= TSP_TSIF_NUM)
5246 {
5247 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u8Path));
5248 return;
5249 }
5250
5251 REG16 *PktConverterReg = &_RegPathCtrl[u8Path].CFG_PATH_05;
5252
5253 if(bEnable)
5254 {
5255 REG16_SET(PktConverterReg, CFG_PATH_05_SRC_ID_FLT_EN);
5256 }
5257 else
5258 {
5259 REG16_CLR(PktConverterReg, CFG_PATH_05_SRC_ID_FLT_EN);
5260 }
5261 }
5262
5263 //-------------------------------------------------------------------------------------------------
5264 // For Debug Table
5265 //-------------------------------------------------------------------------------------------------
5266
HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)5267 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)
5268 {
5269 switch (eFlow)
5270 {
5271 case E_TSP_HAL_FLOW_LIVE0:
5272 return E_TSP_SRC_PKTDMX0;
5273 case E_TSP_HAL_FLOW_LIVE1:
5274 return E_TSP_SRC_PKTDMX2;
5275 case E_TSP_HAL_FLOW_LIVE2:
5276 return E_TSP_SRC_PKTDMX3;
5277 case E_TSP_HAL_FLOW_LIVE3:
5278 return E_TSP_SRC_PKTDMX1;
5279 case E_TSP_HAL_FLOW_FILE0:
5280 return E_TSP_SRC_PKTDMX1;
5281 case E_TSP_HAL_FLOW_FILE1:
5282 return E_TSP_SRC_PKTDMX3;
5283 case E_TSP_HAL_FLOW_FILE2:
5284 return E_TSP_SRC_PKTDMX0;
5285 case E_TSP_HAL_FLOW_FILE3:
5286 return E_TSP_SRC_PKTDMX2;
5287 case E_TSP_HAL_FLOW_LIVE4:
5288 case E_TSP_HAL_FLOW_FILE4:
5289 return E_TSP_SRC_PKTDMX4;
5290 case E_TSP_HAL_FLOW_LIVE5:
5291 case E_TSP_HAL_FLOW_FILE5:
5292 return E_TSP_SRC_PKTDMX5;
5293 case E_TSP_HAL_FLOW_LIVE6:
5294 case E_TSP_HAL_FLOW_FILE6:
5295 return E_TSP_SRC_PKTDMX6;
5296 case E_TSP_HAL_FLOW_MMFI0:
5297 return E_TSP_SRC_MMFI0;
5298 case E_TSP_HAL_FLOW_MMFI1:
5299 return E_TSP_SRC_MMFI1;
5300 default:
5301 printf("[TSP_ERR][%s][%d] UnSupported Debug Flow : %d !!!\n",__FUNCTION__, __LINE__,eFlow);
5302 return E_TSP_SRC_INVALID;
5303 }
5304 }
5305
HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)5306 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)
5307 {
5308 //@NOTE: K7U don't have to implement
5309 }
5310
HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)5311 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf, MS_BOOL bEn)
5312 {
5313 if(u32TsIf >= TSP_TSIF_NUM)
5314 {
5315 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32TsIf));
5316 return;
5317 }
5318
5319 if(bEn)
5320 {
5321 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_02, CFG_PATH_02_REG_LOCKED_PKT_CNT_LOAD);
5322 }
5323 else
5324 {
5325 REG16_CLR(&_RegPathCtrl[u32TsIf].CFG_PATH_02, CFG_PATH_02_REG_LOCKED_PKT_CNT_LOAD);
5326 }
5327 }
5328
HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf,MS_BOOL bLock)5329 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock)
5330 {
5331 if(u32TsIf >= TSP_TSIF_NUM)
5332 {
5333 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32TsIf));
5334 return 0;
5335 }
5336
5337 if(bLock)
5338 {
5339 REG16_CLR(&_RegPathCtrl[u32TsIf].CFG_PATH_02, CFG_PATH_02_REG_UNLOCKED_PKT_CNT_MODE);
5340 }
5341 else
5342 {
5343 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_02, CFG_PATH_02_REG_UNLOCKED_PKT_CNT_MODE);
5344 }
5345
5346 return REG16_R(&_RegPathCtrl[u32TsIf].CFG_PATH_03);
5347 }
5348
HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32TsIf)5349 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32TsIf)
5350 {
5351 if(u32TsIf >= TSP_TSIF_NUM)
5352 {
5353 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32TsIf));
5354 return;
5355 }
5356
5357 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_02, CFG_PATH_02_REG_LOCKED_PKT_CNT_CLR);
5358 REG16_CLR(&_RegPathCtrl[u32TsIf].CFG_PATH_02, CFG_PATH_02_REG_LOCKED_PKT_CNT_CLR);
5359 }
5360
HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)5361 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)
5362 {
5363 //@NOTE: K7U don't have to implement
5364 }
5365
HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)5366 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId)
5367 {
5368 //@NOTE: K7U don't have to implement
5369 }
5370
HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)5371 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn)
5372 {
5373 if((eAvType >= E_TSP_DST_FIFO_AUDIO) && (eAvType <= E_TSP_DST_FIFO_AUDIO6))
5374 {
5375 MS_U8 u8AudioFltIdx = eAvType - E_TSP_DST_FIFO_AUDIO;
5376
5377 if(bEn)
5378 {
5379 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_LOAD);
5380 }
5381 else
5382 {
5383 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_LOAD);
5384 }
5385 }
5386 else if(eAvType <= E_TSP_DST_FIFO_VIDEO8)
5387 {
5388 MS_U8 u8VideoFltIdx = eAvType - E_TSP_DST_FIFO_VIDEO;
5389
5390 if(bEn)
5391 {
5392 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_LOAD);
5393 }
5394 else
5395 {
5396 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_LOAD);
5397 }
5398 }
5399 else
5400 {
5401 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
5402 }
5403 }
5404
HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)5405 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)
5406 {
5407 if((eAvType >= E_TSP_DST_FIFO_AUDIO) && (eAvType <= E_TSP_DST_FIFO_AUDIO6))
5408 {
5409 MS_U8 u8AudioFltIdx = eAvType - E_TSP_DST_FIFO_AUDIO;
5410
5411 return REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_05);
5412 }
5413 else if(eAvType <= E_TSP_DST_FIFO_VIDEO8)
5414 {
5415 MS_U8 u8VideoFltIdx = eAvType - E_TSP_DST_FIFO_VIDEO;
5416
5417 return REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_05);
5418 }
5419 else
5420 {
5421 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
5422 return 0;
5423 }
5424 }
5425
HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)5426 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)
5427 {
5428 if((eAvType >= E_TSP_DST_FIFO_AUDIO) && (eAvType <= E_TSP_DST_FIFO_AUDIO6))
5429 {
5430 MS_U8 u8AudioFltIdx = eAvType - E_TSP_DST_FIFO_AUDIO;
5431
5432 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_CLR);
5433 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_CLR);
5434 }
5435 else if(eAvType <= E_TSP_DST_FIFO_VIDEO8)
5436 {
5437 MS_U8 u8VideoFltIdx = eAvType - E_TSP_DST_FIFO_VIDEO;
5438
5439 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_CLR);
5440 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_PKT_CNT_CLR);
5441 }
5442 else
5443 {
5444 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
5445 }
5446 }
5447
HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)5448 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)
5449 {
5450 //@NOTE: K7U don't have to implement
5451 }
5452
HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)5453 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn)
5454 {
5455 if((eAvType >= E_TSP_DST_FIFO_AUDIO) && (eAvType <= E_TSP_DST_FIFO_AUDIO6))
5456 {
5457 MS_U8 u8AudioFltIdx = eAvType - E_TSP_DST_FIFO_AUDIO;
5458
5459 if(bEn)
5460 {
5461 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_LOAD);
5462 }
5463 else
5464 {
5465 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_LOAD);
5466 }
5467 }
5468 else if(eAvType <= E_TSP_DST_FIFO_VIDEO8)
5469 {
5470 MS_U8 u8VideoFltIdx = eAvType - E_TSP_DST_FIFO_VIDEO;
5471
5472 if(bEn)
5473 {
5474 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_LOAD);
5475 }
5476 else
5477 {
5478 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_LOAD);
5479 }
5480 }
5481 else
5482 {
5483 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
5484 }
5485 }
5486
HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)5487 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)
5488 {
5489 if((eAvType >= E_TSP_DST_FIFO_AUDIO) && (eAvType <= E_TSP_DST_FIFO_AUDIO6))
5490 {
5491 MS_U8 u8AudioFltIdx = eAvType - E_TSP_DST_FIFO_AUDIO;
5492
5493 if(bPayload)
5494 {
5495 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_INC_BY_PL);
5496 }
5497 else
5498 {
5499 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_INC_BY_PL);
5500 }
5501
5502 if(bEn)
5503 {
5504 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_LOAD);
5505 }
5506 else
5507 {
5508 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_LOAD);
5509 }
5510 }
5511 else if(eAvType <= E_TSP_DST_FIFO_VIDEO8)
5512 {
5513 MS_U8 u8VideoFltIdx = eAvType - E_TSP_DST_FIFO_VIDEO;
5514
5515 if(bPayload)
5516 {
5517 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_INC_BY_PL);
5518 }
5519 else
5520 {
5521 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_INC_BY_PL);
5522 }
5523
5524 if(bEn)
5525 {
5526 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_LOAD);
5527 }
5528 else
5529 {
5530 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_LOAD);
5531 }
5532 }
5533 else
5534 {
5535 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
5536 }
5537 }
5538
HAL_TSP_Debug_DropDisPktCnt_Get(TSP_DST_SEQ eAvType,MS_BOOL bDrop)5539 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_DST_SEQ eAvType, MS_BOOL bDrop)
5540 {
5541 if((eAvType >= E_TSP_DST_FIFO_AUDIO) && (eAvType <= E_TSP_DST_FIFO_AUDIO6))
5542 {
5543 MS_U8 u8AudioFltIdx = eAvType - E_TSP_DST_FIFO_AUDIO;
5544
5545 if(bDrop)
5546 {
5547 return REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_03);
5548 }
5549 else
5550 {
5551 return REG16_R(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_04);
5552 }
5553 }
5554 else if(eAvType <= E_TSP_DST_FIFO_VIDEO8)
5555 {
5556 MS_U8 u8VideoFltIdx = eAvType - E_TSP_DST_FIFO_VIDEO;
5557
5558 if(bDrop)
5559 {
5560 return REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_03);
5561 }
5562 else
5563 {
5564 return REG16_R(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_04);
5565 }
5566 }
5567 else
5568 {
5569 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
5570 return 0;
5571 }
5572 }
5573
HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)5574 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)
5575 {
5576 if((eAvType >= E_TSP_DST_FIFO_AUDIO) && (eAvType <= E_TSP_DST_FIFO_AUDIO6))
5577 {
5578 MS_U8 u8AudioFltIdx = eAvType - E_TSP_DST_FIFO_AUDIO;
5579
5580 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_CLR);
5581 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_CLR);
5582 }
5583 else if(eAvType <= E_TSP_DST_FIFO_VIDEO8)
5584 {
5585 MS_U8 u8VideoFltIdx = eAvType - E_TSP_DST_FIFO_VIDEO;
5586
5587 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_CLR);
5588 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DROP_PKT_CNT_CLR);
5589 }
5590 else
5591 {
5592 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
5593 }
5594 }
5595
HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)5596 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)
5597 {
5598 if((eAvType >= E_TSP_DST_FIFO_AUDIO) && (eAvType <= E_TSP_DST_FIFO_AUDIO6))
5599 {
5600 MS_U8 u8AudioFltIdx = eAvType - E_TSP_DST_FIFO_AUDIO;
5601
5602 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_CLR);
5603 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_CLR);
5604 }
5605 else if(eAvType <= E_TSP_DST_FIFO_VIDEO8)
5606 {
5607 MS_U8 u8VideoFltIdx = eAvType - E_TSP_DST_FIFO_VIDEO;
5608
5609 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_CLR);
5610 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_02, CFG_AV_02_REG_DIS_CNTR_CLR);
5611 }
5612 else
5613 {
5614 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[AV ERROR][%s][%d] Type not support !!\n",__FUNCTION__,__LINE__));
5615 }
5616 }
5617
5618 #if FPGA_TEST
5619
HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)5620 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)
5621 {
5622 //@NOTE: K7U don't have to implement
5623 }
5624
HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)5625 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf, MS_BOOL bEn)
5626 {
5627 if(u32TsIf >= TSP_TSIF_NUM)
5628 {
5629 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32TsIf));
5630 return;
5631 }
5632
5633 if(bEn)
5634 {
5635 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_0C, CFG_PATH_0C_REG_ERR_PKT_CNTR_LOAD);
5636 }
5637 else
5638 {
5639 REG16_CLR(&_RegPathCtrl[u32TsIf].CFG_PATH_0C, CFG_PATH_0C_REG_ERR_PKT_CNTR_LOAD);
5640 }
5641 }
5642
HAL_TSP_Debug_ErrPktCnt_Get(MS_U32 u32TsIf)5643 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(MS_U32 u32TsIf)
5644 {
5645 if(u32TsIf >= TSP_TSIF_NUM)
5646 {
5647 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32TsIf));
5648 return 0;
5649 }
5650
5651 return REG16_R(&_RegPathCtrl[u32TsIf].CFG_PATH_0B);
5652 }
5653
HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32TsIf)5654 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32TsIf)
5655 {
5656 if(u32TsIf >= TSP_TSIF_NUM)
5657 {
5658 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong Path Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32TsIf));
5659 return;
5660 }
5661
5662 REG16_SET(&_RegPathCtrl[u32TsIf].CFG_PATH_0C, CFG_PATH_0C_REG_ERR_PKT_CNTR_CLR);
5663 REG16_CLR(&_RegPathCtrl[u32TsIf].CFG_PATH_0C, CFG_PATH_0C_REG_ERR_PKT_CNTR_CLR);
5664 }
5665
HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)5666 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)
5667 {
5668 //@NOTE: K7U don't have to implement (deleted...)
5669 }
5670
HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)5671 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
5672 {
5673 //@NOTE: K7U don't have to implement (deleted...)
5674 }
5675
HAL_TSP_Debug_InputPktCnt_Get(void)5676 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void)
5677 {
5678 //@NOTE: K7U don't have to implement (deleted...)
5679 return 0;
5680 }
5681
HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)5682 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)
5683 {
5684 //@NOTE: K7U don't have to implement (deleted...)
5685 }
5686
5687 #endif
5688
HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng,MS_U32 u32FQSrc)5689 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc)
5690 {
5691 // not support
5692 return TRUE;
5693 }
5694
HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)5695 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)
5696 {
5697 // not support
5698 return 0;
5699 }
5700
HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng,MS_BOOL bFltNull)5701 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull)
5702 {
5703 if(u32FQEng >= TSP_FQ_NUM)
5704 {
5705 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FQ Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32FQEng));
5706 return FALSE;
5707 }
5708
5709 if(bFltNull)
5710 {
5711 REG16_SET(&_RegPathCtrl[u32FQEng].CFG_PATH_06, CFG_PATH_06_REG_FILTER_NULL_PKT);
5712 }
5713 else
5714 {
5715 REG16_CLR(&_RegPathCtrl[u32FQEng].CFG_PATH_06, CFG_PATH_06_REG_FILTER_NULL_PKT);
5716 }
5717
5718 return TRUE;
5719 }
5720
HAL_TSP_FQ_MuxOutPathSrc(MS_U32 u32FQEng,TSP_FQ_MUX_OUT_SRC * peSrc,MS_BOOL bSet)5721 MS_BOOL HAL_TSP_FQ_MuxOutPathSrc(MS_U32 u32FQEng, TSP_FQ_MUX_OUT_SRC *peSrc, MS_BOOL bSet)
5722 {
5723 if(u32FQEng >= TSP_FQ_NUM)
5724 {
5725 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP_ERR][%s][%d] Wrong FQ Engine : 0x%x !!\n",__FUNCTION__,__LINE__,u32FQEng));
5726 return FALSE;
5727 }
5728
5729 if(bSet)
5730 {
5731 REG16_MSK_W(&_RegPathCtrl[u32FQEng].CFG_PATH_09, CFG_PATH_09_REG_FIQ_MUX_OUT_PATH_SRC_MASK, ((MS_U16)*peSrc << CFG_PATH_09_REG_FIQ_MUX_OUT_PATH_SRC_SHIFT));
5732 }
5733 else
5734 {
5735 *peSrc = (TSP_FQ_MUX_OUT_SRC)((REG16_R(&_RegPathCtrl[u32FQEng].CFG_PATH_09) & CFG_PATH_09_REG_FIQ_MUX_OUT_PATH_SRC_MASK) >> CFG_PATH_09_REG_FIQ_MUX_OUT_PATH_SRC_SHIFT);
5736 }
5737
5738 return TRUE;
5739 }
5740
HAL_TSP_CLK_GATING(TSP_HAL_GATING ePath,MS_U32 u32Eng,MS_BOOL bEn)5741 void HAL_TSP_CLK_GATING(TSP_HAL_GATING ePath, MS_U32 u32Eng, MS_BOOL bEn)
5742 {
5743 #if 0 //@NOTE: temporarily comment
5744 if(bEn)
5745 {
5746 switch(ePath)
5747 {
5748 case E_TSP_HAL_GATING_PATH0:
5749 case E_TSP_HAL_GATING_PATH1:
5750 case E_TSP_HAL_GATING_PATH2:
5751 case E_TSP_HAL_GATING_PATH3:
5752 case E_TSP_HAL_GATING_PATH4:
5753 case E_TSP_HAL_GATING_PATH5:
5754 if(u32Eng > TSP_TSIF_NUM)
5755 {
5756 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5757 return;
5758 }
5759 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PATH0 << u32Eng);
5760 break;
5761
5762 case E_TSP_HAL_GATING_TSP_ENG:
5763 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_TSP_ENG);
5764 break;
5765 case E_TSP_HAL_GATING_FIQ:
5766 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_FIQ);
5767 break;
5768
5769 case E_TSP_HAL_GATING_PVR1:
5770 case E_TSP_HAL_GATING_PVR2:
5771 case E_TSP_HAL_GATING_PVR3:
5772 case E_TSP_HAL_GATING_PVR4:
5773 if(u32Eng > TSP_PVRENG_NUM)
5774 {
5775 printf("[%s][%s][%d] UnSupported PVR eng : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5776 return;
5777 }
5778 REG16_SET(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PVR1 << u32Eng);
5779 break;
5780
5781 case E_TSP_HAL_MIU_CLK_GATING_PATH0:
5782 case E_TSP_HAL_MIU_CLK_GATING_PATH1:
5783 case E_TSP_HAL_MIU_CLK_GATING_PATH2:
5784 case E_TSP_HAL_MIU_CLK_GATING_PATH3:
5785 case E_TSP_HAL_MIU_CLK_GATING_PATH4:
5786 case E_TSP_HAL_MIU_CLK_GATING_PATH5:
5787 if(u32Eng > TSP_TSIF_NUM)
5788 {
5789 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5790 return;
5791 }
5792 REG16_SET(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_PATH0 << u32Eng);
5793 break;
5794
5795 case E_TSP_HAL_MIU_CLK_GATING_TSP_ENG:
5796 REG16_SET(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_TSP_ENG);
5797 break;
5798
5799 case E_TSP_HAL_GATING_FIQ0:
5800 case E_TSP_HAL_GATING_FIQ1:
5801 case E_TSP_HAL_GATING_FIQ2:
5802 case E_TSP_HAL_GATING_FIQ3:
5803 case E_TSP_HAL_GATING_FIQ4:
5804 case E_TSP_HAL_GATING_FIQ5:
5805 if(u32Eng > TSP_FQ_NUM)
5806 {
5807 printf("[%s][%s][%d] UnSupported FIQ : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5808 return;
5809 }
5810 REG16_SET(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_CLK_GATING_FIQ0 << u32Eng);
5811 break;
5812
5813 case E_TSP_HAL_MIU_CLK_GATING_FIQ0:
5814 case E_TSP_HAL_MIU_CLK_GATING_FIQ1:
5815 case E_TSP_HAL_MIU_CLK_GATING_FIQ2:
5816 case E_TSP_HAL_MIU_CLK_GATING_FIQ3:
5817 case E_TSP_HAL_MIU_CLK_GATING_FIQ4:
5818 case E_TSP_HAL_MIU_CLK_GATING_FIQ5:
5819 if(u32Eng > TSP_FQ_NUM)
5820 {
5821 printf("[%s][%s][%d] UnSupported FIQ : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5822 return;
5823 }
5824 REG16_SET(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_MIU_CLK_GATING_FIQ0 << u32Eng);
5825 break;
5826 default :
5827 printf("[%s][%s][%d] UnSupported Type : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)ePath);
5828 break;
5829 }
5830 }
5831 else
5832 {
5833 switch(ePath)
5834 {
5835 case E_TSP_HAL_GATING_PATH0:
5836 case E_TSP_HAL_GATING_PATH1:
5837 case E_TSP_HAL_GATING_PATH2:
5838 case E_TSP_HAL_GATING_PATH3:
5839 case E_TSP_HAL_GATING_PATH4:
5840 case E_TSP_HAL_GATING_PATH5:
5841 if(u32Eng > TSP_TSIF_NUM)
5842 {
5843 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5844 return;
5845 }
5846 REG16_CLR(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PATH0 << u32Eng);
5847 break;
5848
5849 case E_TSP_HAL_GATING_TSP_ENG:
5850 REG16_CLR(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_TSP_ENG);
5851 break;
5852 case E_TSP_HAL_GATING_FIQ:
5853 REG16_CLR(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_FIQ);
5854 break;
5855
5856 case E_TSP_HAL_GATING_PVR1:
5857 case E_TSP_HAL_GATING_PVR2:
5858 case E_TSP_HAL_GATING_PVR3:
5859 case E_TSP_HAL_GATING_PVR4:
5860 if(u32Eng > TSP_PVRENG_NUM)
5861 {
5862 printf("[%s][%s][%d] UnSupported PVR eng : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5863 return;
5864 }
5865 REG16_CLR(&_RegCtrl6->CFG6_79,CFG6_79_REG_CLK_GATING_PVR1 << u32Eng);
5866 break;
5867
5868 case E_TSP_HAL_MIU_CLK_GATING_PATH0:
5869 case E_TSP_HAL_MIU_CLK_GATING_PATH1:
5870 case E_TSP_HAL_MIU_CLK_GATING_PATH2:
5871 case E_TSP_HAL_MIU_CLK_GATING_PATH3:
5872 case E_TSP_HAL_MIU_CLK_GATING_PATH4:
5873 case E_TSP_HAL_MIU_CLK_GATING_PATH5:
5874 if(u32Eng > TSP_TSIF_NUM)
5875 {
5876 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5877 return;
5878 }
5879
5880 REG16_CLR(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_PATH0 << u32Eng);
5881 break;
5882
5883 case E_TSP_HAL_MIU_CLK_GATING_TSP_ENG:
5884 REG16_CLR(&_RegCtrl6->CFG6_7F,CFG6_7F_REG_MIU_CLK_GATING_TSP_ENG);
5885 break;
5886
5887 case E_TSP_HAL_GATING_FIQ0:
5888 case E_TSP_HAL_GATING_FIQ1:
5889 case E_TSP_HAL_GATING_FIQ2:
5890 case E_TSP_HAL_GATING_FIQ3:
5891 case E_TSP_HAL_GATING_FIQ4:
5892 case E_TSP_HAL_GATING_FIQ5:
5893 if(u32Eng > TSP_FQ_NUM)
5894 {
5895 printf("[%s][%s][%d] UnSupported FIQ : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5896 return;
5897 }
5898 REG16_CLR(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_CLK_GATING_FIQ0 << u32Eng);
5899 break;
5900
5901 case E_TSP_HAL_MIU_CLK_GATING_FIQ0:
5902 case E_TSP_HAL_MIU_CLK_GATING_FIQ1:
5903 case E_TSP_HAL_MIU_CLK_GATING_FIQ2:
5904 case E_TSP_HAL_MIU_CLK_GATING_FIQ3:
5905 case E_TSP_HAL_MIU_CLK_GATING_FIQ4:
5906 case E_TSP_HAL_MIU_CLK_GATING_FIQ5:
5907 if(u32Eng > TSP_FQ_NUM)
5908 {
5909 printf("[%s][%s][%d] UnSupported FIQ : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Eng);
5910 return;
5911 }
5912 REG16_CLR(&_RegCtrl6->CFG6_6D,CFG6_6D_REG_MIU_CLK_GATING_FIQ1 << u32Eng);
5913 break;
5914
5915 default :
5916 printf("[%s][%s][%d] UnSupported Type : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)ePath);
5917 break;
5918 }
5919 }
5920 #endif
5921 }
5922
HAL_TSP_Module_Reset(TSP_HAL_RESET_CTRL ePath,MS_U32 u32Idx,MS_BOOL bEn)5923 void HAL_TSP_Module_Reset(TSP_HAL_RESET_CTRL ePath, MS_U32 u32Idx, MS_BOOL bEn)
5924 {
5925 #if 0 //@NOTE: temporarily comment
5926 if(bEn)
5927 {
5928 switch(ePath)
5929 {
5930 case E_TSP_HAL_RESET_CTRL_PKT_CONVERTER0:
5931 if(u32Idx > TSP_TSIF_NUM)
5932 return;
5933 REG16_SET(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_PKT_CONVERTER0 << u32Idx);
5934 break;
5935 case E_TSP_HAL_RESET_CTRL_FIQ0:
5936 if(u32Idx > TSP_TSIF_NUM)
5937 return;
5938 REG16_SET(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_FIQ0 << u32Idx);
5939 break;
5940 case E_TSP_HAL_RESET_CTRL_VQ_TX0:
5941 if(u32Idx > TSP_TSIF_NUM)
5942 return;
5943 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TX0 << u32Idx);
5944 break;
5945 case E_TSP_HAL_RESET_CTRL_VQ_RX:
5946 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_RX);
5947 break;
5948 case E_TSP_HAL_RESET_CTRL_VQ_TOP:
5949 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TOP);
5950 break;
5951 case E_TSP_HAL_RESET_CTRL_PKT_DEMUX0:
5952 if(u32Idx > TSP_TSIF_NUM)
5953 return;
5954 REG16_SET(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_PKT_DEMUX0 << u32Idx);
5955 break;
5956 case E_TSP_HAL_RESET_CTRL_PVR1:
5957 if(u32Idx > TSP_TSIF_NUM)
5958 return;
5959 REG16_SET(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_PVR1 << u32Idx);
5960 break;
5961 case E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR1:
5962 if(u32Idx > TSP_TSIF_NUM)
5963 return;
5964 REG16_SET(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_TIMESTAMP_SEL_PVR1 << u32Idx);
5965 break;
5966 case E_TSP_HAL_RESET_CTRL_SP_D0:
5967 if(u32Idx > TSP_TSIF_NUM)
5968 return;
5969 REG16_SET(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_SP_D0 << u32Idx);
5970 break;
5971 case E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT0:
5972 if(u32Idx > TSP_TSIF_NUM)
5973 return;
5974 REG16_SET(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_FILTER_NULL_PKT0 << u32Idx);
5975 break;
5976 case E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_0:
5977 if(u32Idx > TSP_TSIF_NUM)
5978 return;
5979 REG16_SET(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_DIRECTV_130_188_0 << u32Idx);
5980 break;
5981 case E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER0:
5982 if(u32Idx > TSP_TSIF_NUM)
5983 return;
5984 REG16_SET(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_SRC_ID_PARSER0 << u32Idx);
5985 break;
5986 case E_TSP_HAL_RESET_CTRL_PCRFLT_0:
5987 if(u32Idx > TSP_TSIF_NUM)
5988 return;
5989 REG16_SET(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_PCRFLT_0 << u32Idx);
5990 break;
5991 case E_TSP_HAL_RESET_PATH0:
5992 if(u32Idx > TSP_TSIF_NUM)
5993 return;
5994 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PATH0 << u32Idx);
5995 break;
5996 case E_TSP_HAL_RESET_OTV:
5997 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_OTV);
5998 break;
5999 case E_TSP_HAL_RESET_DEBUG_TABLE:
6000 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DEBUG_TABLE);
6001 break;
6002 case E_TSP_HAL_RESET_DMA_ENG:
6003 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DMA_ENG);
6004 break;
6005 case E_TSP_HAL_RESET_SEC_CMP:
6006 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC_CMP);
6007 break;
6008 case E_TSP_HAL_RESET_SECFLT_REG:
6009 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SECFLT_REG);
6010 break;
6011 case E_TSP_HAL_RESET_SEC:
6012 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC);
6013 break;
6014 case E_TSP_HAL_RESET_PID_TABLE:
6015 REG16_SET(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PID_TABLE);
6016 break;
6017
6018 default :
6019 printf("[%s][%s][%d] UnSupported Type : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)ePath);
6020 break;
6021 }
6022 }
6023 else
6024 {
6025 switch(ePath)
6026 {
6027 case E_TSP_HAL_RESET_CTRL_PKT_CONVERTER0:
6028 if(u32Idx > TSP_TSIF_NUM)
6029 return;
6030 REG16_CLR(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_PKT_CONVERTER0 << u32Idx);
6031 break;
6032 case E_TSP_HAL_RESET_CTRL_FIQ0:
6033 if(u32Idx > TSP_TSIF_NUM)
6034 return;
6035 REG16_CLR(&_RegCtrl6->CFG6_7A,CFG6_7A_REG_CLK_RESET_FIQ0 << u32Idx);
6036 break;
6037 case E_TSP_HAL_RESET_CTRL_VQ_TX0:
6038 if(u32Idx > TSP_TSIF_NUM)
6039 return;
6040 REG16_CLR(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TX0 << u32Idx);
6041 break;
6042 case E_TSP_HAL_RESET_CTRL_VQ_RX:
6043 REG16_CLR(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_RX);
6044 break;
6045 case E_TSP_HAL_RESET_CTRL_VQ_TOP:
6046 REG16_CLR(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_VQ_TOP);
6047 break;
6048 case E_TSP_HAL_RESET_CTRL_PKT_DEMUX0:
6049 if(u32Idx > TSP_TSIF_NUM)
6050 return;
6051 REG16_CLR(&_RegCtrl6->CFG6_7B,CFG6_7B_REG_RESET_PKT_DEMUX0 << u32Idx);
6052 break;
6053 case E_TSP_HAL_RESET_CTRL_PVR1:
6054 if(u32Idx > TSP_TSIF_NUM)
6055 return;
6056 REG16_CLR(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_PVR1 << u32Idx);
6057 break;
6058 case E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR1:
6059 if(u32Idx > TSP_TSIF_NUM)
6060 return;
6061 REG16_CLR(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_TIMESTAMP_SEL_PVR1 << u32Idx);
6062 break;
6063 case E_TSP_HAL_RESET_CTRL_SP_D0:
6064 if(u32Idx > TSP_TSIF_NUM)
6065 return;
6066 REG16_CLR(&_RegCtrl6->CFG6_7C,CFG6_7C_REG_RESET_SP_D0 << u32Idx);
6067 break;
6068 case E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT0:
6069 if(u32Idx > TSP_TSIF_NUM)
6070 return;
6071 REG16_CLR(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_FILTER_NULL_PKT0 << u32Idx);
6072 break;
6073 case E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_0:
6074 if(u32Idx > TSP_TSIF_NUM)
6075 return;
6076 REG16_CLR(&_RegCtrl6->CFG6_7D,CFG6_7D_REG_RESET_DIRECTV_130_188_0 << u32Idx);
6077 break;
6078 case E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER0:
6079 if(u32Idx > TSP_TSIF_NUM)
6080 return;
6081 REG16_CLR(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_SRC_ID_PARSER0 << u32Idx);
6082 break;
6083 case E_TSP_HAL_RESET_CTRL_PCRFLT_0:
6084 if(u32Idx > TSP_TSIF_NUM)
6085 return;
6086 REG16_CLR(&_RegCtrl6->CFG6_7E,CFG6_7E_REG_RESET_PCRFLT_0 << u32Idx);
6087 break;
6088 case E_TSP_HAL_RESET_PATH0:
6089 if(u32Idx > TSP_TSIF_NUM)
6090 return;
6091 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PATH0 << u32Idx);
6092 break;
6093 case E_TSP_HAL_RESET_OTV:
6094 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_OTV);
6095 break;
6096 case E_TSP_HAL_RESET_DEBUG_TABLE:
6097 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DEBUG_TABLE);
6098 break;
6099 case E_TSP_HAL_RESET_DMA_ENG:
6100 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_DMA_ENG);
6101 break;
6102 case E_TSP_HAL_RESET_SEC_CMP:
6103 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC_CMP);
6104 break;
6105 case E_TSP_HAL_RESET_SECFLT_REG:
6106 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SECFLT_REG);
6107 break;
6108 case E_TSP_HAL_RESET_SEC:
6109 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_SEC);
6110 break;
6111 case E_TSP_HAL_RESET_PID_TABLE:
6112 REG16_CLR(&_RegCtrl6->CFG6_6C,CFG6_6C_REG_RESET_PID_TABLE);
6113 break;
6114
6115 default :
6116 printf("[%s][%s][%d] UnSupported Type : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)ePath);
6117 break;
6118 }
6119 }
6120 #endif
6121 }
6122
HAL_TSP_PidFlt_SetLutEn(MS_U32 fltId,MS_BOOL bEn)6123 void HAL_TSP_PidFlt_SetLutEn(MS_U32 fltId, MS_BOOL bEn)
6124 {
6125 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
6126
6127 if(bEn)
6128 {
6129 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) | TSP_PIDFLT_OUT_LUT));
6130 }
6131 else
6132 {
6133 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_OUT_LUT));
6134 }
6135 }
6136
HAL_TSP_PidFlt_SetFqLutEn(MS_U32 fltId,MS_U32 u32FqLutEng,MS_BOOL bEn)6137 void HAL_TSP_PidFlt_SetFqLutEn(MS_U32 fltId, MS_U32 u32FqLutEng, MS_BOOL bEn)
6138 {
6139 REG_PidFlt *pPidFlt = PPIDFLT2(fltId);
6140
6141 if(bEn)
6142 {
6143 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_FIQ_LUT_MASK) | (((1 << u32FqLutEng) << TSP_PIDFLT_FIQ_LUT_SHIFT) & TSP_PIDFLT_FIQ_LUT_MASK));
6144 }
6145 else
6146 {
6147 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_FIQ_LUT_MASK));
6148 }
6149 }
6150
HAL_TSP_PidFlt_SetMultiPvrEn(MS_U32 fltId,MS_U32 u32MultiPvrEng,MS_U32 u32MultiPvrChId,MS_BOOL bEn)6151 void HAL_TSP_PidFlt_SetMultiPvrEn(MS_U32 fltId, MS_U32 u32MultiPvrEng, MS_U32 u32MultiPvrChId, MS_BOOL bEn)
6152 {
6153 REG_PidFlt *pPidFlt = PPIDFLT2(fltId);
6154
6155 if(bEn)
6156 {
6157 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_MULTI_PVR_MASK) | (((1 << u32MultiPvrChId) << TSP_PIDFLT_MULTI_PVR_SHIFT) & TSP_PIDFLT_MULTI_PVR_MASK));
6158 }
6159 else
6160 {
6161 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_MULTI_PVR_MASK));
6162 }
6163 }
6164
HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType,MS_U8 u8Eng,MS_PHY phyBufStart)6165 void HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType, MS_U8 u8Eng, MS_PHY phyBufStart)
6166 {
6167 MS_U8 u8MiuSel = 0;
6168 MS_PHY phyMiuOffsetFileinAddr = 0;
6169 MS_U8 u8Shift = 0;
6170
6171 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinAddr, phyBufStart);
6172
6173 switch(eType)
6174 {
6175 case E_TSP_HAL_MIU_SEL_MMFI:
6176 u8Shift = u8Eng * TSP_MIU_SEL_BITS_LEN;
6177 REG16_MSK_W(&_RegTopCtrl->CFG_TOP_09, (CFG_TOP_09_REG_MIU_SEL_MMFI_MASK << u8Shift), (u8MiuSel << (CFG_TOP_09_REG_MIU_SEL_MMFI_SHIFT + u8Shift)));
6178 break;
6179 case E_TSP_HAL_MIU_SEL_FQ:
6180 if(u8Eng < TSP_FQ_MUX_START_ID)
6181 {
6182 u8Shift = u8Eng * TSP_MIU_SEL_BITS_LEN;
6183 REG16_MSK_W(&_RegTopCtrl->CFG_TOP_07, (CFG_TOP_07_REG_MIU_SEL_FIQ_MASK << u8Shift), (u8MiuSel << (CFG_TOP_07_REG_MIU_SEL_FIQ_SHIFT + u8Shift)));
6184 }
6185 else
6186 {
6187 u8Shift = (u8Eng - TSP_FQ_MUX_START_ID) * TSP_MIU_SEL_BITS_LEN;
6188 REG16_MSK_W(&_RegTopCtrl->CFG_TOP_09, (CFG_TOP_09_REG_MIU_SEL_FIQ_MUX_MASK << u8Shift), (u8MiuSel << (CFG_TOP_09_REG_MIU_SEL_FIQ_MUX_SHIFT + u8Shift)));
6189 }
6190 break;
6191 default:
6192 break;
6193 }
6194 }
6195