Lines Matching refs:MIU_BUS
147 #define MIU_BUS (4) macro
312 u32WritePtr = u32WritePtr + (1 << MIU_BUS); in _Adjust_PVR_WritePtr()
321 u32WritePtr = u32WritePtr + (1 << MIU_BUS); in _Adjust_PVR_WritePtr()
766 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT; in HAL_TSP_LoadFW()
4391 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment in HAL_TSP_SetVQ()
4419 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4423 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4427 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4431 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS)); in HAL_TSP_VQ_Buffer()
4912 … REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
4914 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
4916 …REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
4919 …REG32_W(&_RegCtrl->Str2mi_head2pvr1, (phyMiuOffsetPvrBuf1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetBuf()
4921 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetBuf()
4923 … REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK); in HAL_PVR_SetBuf()
4930 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
4932 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
4934 …REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MAS… in HAL_PVR_SetBuf()
4937 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (phyMiuOffsetPvrBuf1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
4939 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
4941 … REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (phyMiuOffsetPvrBuf1 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetBuf()
4948 … REG32_W(&(_RegCtrl2->CFG_17_18), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD); in HAL_PVR_SetBuf()
4950 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0 >> MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL); in HAL_PVR_SetBuf()
4952 … REG32_W(&(_RegCtrl2->CFG_19_1A), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_19_1A_PVR3_STR2MI_MID); in HAL_PVR_SetBuf()
4955 … REG32_W(&(_RegCtrl2->CFG_1D_1E), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2); in HAL_PVR_SetBuf()
4957 … REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1 >> MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2); in HAL_PVR_SetBuf()
4959 … REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2); in HAL_PVR_SetBuf()
4966 … REG32_W(&(_RegCtrl2->CFG_24_25), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD); in HAL_PVR_SetBuf()
4968 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL); in HAL_PVR_SetBuf()
4970 … REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID); in HAL_PVR_SetBuf()
4973 … REG32_W(&(_RegCtrl2->CFG_2A_2B), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2); in HAL_PVR_SetBuf()
4975 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2); in HAL_PVR_SetBuf()
4977 … REG32_W(&(_RegCtrl2->CFG_2C_2D), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2C_2D_PVR4_STR2MI_MID2); in HAL_PVR_SetBuf()
4992 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
4995 … REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
4999 … REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5002 … REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_StartAddr()
5007 REG32_W(&(_RegCtrl2->CFG_17_18), (u32StartAddr0>>MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD); in HAL_PVR_SetStr2Miu_StartAddr()
5010 … REG32_W(&(_RegCtrl2->CFG_1D_1E), (u32StartAddr1>>MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2); in HAL_PVR_SetStr2Miu_StartAddr()
5014 REG32_W(&(_RegCtrl2->CFG_24_25), (u32StartAddr0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD); in HAL_PVR_SetStr2Miu_StartAddr()
5017 … REG32_W(&(_RegCtrl2->CFG_2A_2B), (u32StartAddr1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2); in HAL_PVR_SetStr2Miu_StartAddr()
5087 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5090 … REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5094 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5097 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK); in HAL_PVR_SetStr2Miu_EndAddr()
5101 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0>>MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL); in HAL_PVR_SetStr2Miu_EndAddr()
5104 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1>>MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2); in HAL_PVR_SetStr2Miu_EndAddr()
5108 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL); in HAL_PVR_SetStr2Miu_EndAddr()
5111 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2); in HAL_PVR_SetStr2Miu_EndAddr()
5131 WritePtr = REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS; in HAL_PVR_GetWritePtr()
5134 WritePtr = REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS; in HAL_PVR_GetWritePtr()
5137 WritePtr = REG32_R(&(_RegCtrl2->CFG_66_67)) << MIU_BUS; in HAL_PVR_GetWritePtr()
5140 WritePtr = REG32_R(&(_RegCtrl2->CFG_68_69)) << MIU_BUS; in HAL_PVR_GetWritePtr()
6554 …REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_LB… in HAL_TSP_OR_Address_Protect()
6555 …REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_UB… in HAL_TSP_OR_Address_Protect()
6574 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_DMAW_BND_MASK); in HAL_TSP_SEC_Address_Protect()
6575 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_DMAW_BND_MASK); in HAL_TSP_SEC_Address_Protect()
6639 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_PVR_MASK); in HAL_TSP_PVR_Address_Protect()
6640 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_PVR_MASK); in HAL_TSP_PVR_Address_Protect()
6712 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK); in HAL_TSP_FILEIN_Address_Protect()
6713 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK); in HAL_TSP_FILEIN_Address_Protect()
6773 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK); in HAL_TSP_MMFI_Address_Protect()
6774 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK); in HAL_TSP_MMFI_Address_Protect()