127 #define MIU_BUS (4)  macro
670     u32DnldCtrl  =      (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT;  in HAL_TSP_LoadFW()
1428             MS_U32  u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK);  in HAL_TSP_FILEIN_Address_Protect()
1429             MS_U32  u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK);  in HAL_TSP_FILEIN_Address_Protect()
3231     u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment  in HAL_TSP_SetVQ()
3258     REG32_W(&_RegOtherCtrl->CFG_OTHER_30_67[vqId].reg_vq_base, (u32BaseAddr >> MIU_BUS));  in HAL_TSP_VQ_Buffer()
3665         REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_01_02, (u32StartAddr0 >> MIU_BUS));  in HAL_PVR_SetBuf()
3667         REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_05_06, (u32EndAddr0 >> MIU_BUS));  in HAL_PVR_SetBuf()
3669         REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_03_04, (u32StartAddr0 >> MIU_BUS));  in HAL_PVR_SetBuf()
3672         REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_07_08, (u32StartAddr1 >> MIU_BUS));  in HAL_PVR_SetBuf()
3674         REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_0B_0C, (u32EndAddr1 >> MIU_BUS));  in HAL_PVR_SetBuf()
3676         REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_09_0A, (u32StartAddr1 >> MIU_BUS));  in HAL_PVR_SetBuf()
3704     REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_01_02, (phyMiuOffsetPvrBuf0 >> MIU_BUS));  in HAL_PVR_SetStr2Miu_StartAddr()
3706     REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_07_08, (phyMiuOffsetPvrBuf1 >> MIU_BUS));  in HAL_PVR_SetStr2Miu_StartAddr()
3733     REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_03_04, (phyMiuOffsetPvrBuf0 >> MIU_BUS));  in HAL_PVR_SetStr2Miu_MidAddr()
3735     REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_09_0A, (phyMiuOffsetPvrBuf1 >> MIU_BUS));  in HAL_PVR_SetStr2Miu_MidAddr()
3762     REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_05_06, (u32EndAddr0 >> MIU_BUS));  in HAL_PVR_SetStr2Miu_EndAddr()
3764     REG32_W(&RegPvrCtrl[u8PvrEng].CFG_PVR_0B_0C, (u32EndAddr1 >> MIU_BUS));  in HAL_PVR_SetStr2Miu_EndAddr()
3778     return (REG32_R(&RegPvrCtrl[u8PvrEng].CFG_PVR_13_14) << MIU_BUS);  in HAL_PVR_GetWritePtr()
4731 …  REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK));  in HAL_TSP_OR_Address_Protect()
4732 …  REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK));  in HAL_TSP_OR_Address_Protect()
4758         MS_U32  u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & TSP_DMAW_BND_MASK);  in HAL_TSP_SEC_Address_Protect()
4759         MS_U32  u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & TSP_DMAW_BND_MASK);  in HAL_TSP_SEC_Address_Protect()
4817         MS_U32  u32LBnd = (MS_U32)(phyMiuOffsetLB >> MIU_BUS);  in HAL_TSP_PVR_Address_Protect()
4818         MS_U32  u32UBnd = (MS_U32)(phyMiuOffsetUB >> MIU_BUS);  in HAL_TSP_PVR_Address_Protect()
4859         MS_U32  u32LBnd = (MS_U32)((phyMiuOffsetLB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK);  in HAL_TSP_MMFI_Address_Protect()
4860         MS_U32  u32UBnd = (MS_U32)((phyMiuOffsetUB >> MIU_BUS) & REG_TOP_ProtectCtrl_BND_MASK);  in HAL_TSP_MMFI_Address_Protect()