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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3036.h12 u32 scfg;
13 u32 sctl;
14 u32 stat;
15 u32 intrstat;
16 u32 reserved0[12];
17 u32 mcmd;
18 u32 powctl;
19 u32 powstat;
20 u32 cmdtstat;
21 u32 cmdtstaten;
[all …]
H A Dddr_rk3368.h16 u32 scfg;
17 u32 sctl;
18 u32 stat;
19 u32 intrstat;
20 u32 reserved0[12];
21 u32 mcmd;
22 u32 powctl;
23 u32 powstat;
24 u32 cmdtstat;
25 u32 cmdtstaten;
[all …]
H A Dgrf_rv1108.h13 u32 reserved[4];
14 u32 gpio1a_iomux;
15 u32 gpio1b_iomux;
16 u32 gpio1c_iomux;
17 u32 gpio1d_iomux;
18 u32 gpio2a_iomux;
19 u32 gpio2b_iomux;
20 u32 gpio2c_iomux;
21 u32 gpio2d_iomux;
22 u32 gpio3a_iomux;
[all …]
H A Dgrf_rk3328.h11 u32 gpio0a_iomux;
12 u32 gpio0b_iomux;
13 u32 gpio0c_iomux;
14 u32 gpio0d_iomux;
15 u32 gpio1a_iomux;
16 u32 gpio1b_iomux;
17 u32 gpio1c_iomux;
18 u32 gpio1d_iomux;
19 u32 gpio2a_iomux;
20 u32 gpio2bl_iomux;
[all …]
H A Dsdram_rv1108_pctl_phy.h13 u32 scfg;
14 u32 sctl;
15 u32 stat;
16 u32 intrstat;
17 u32 reserved0[(0x40 - 0x10) / 4];
18 u32 mcmd;
19 u32 powctl;
20 u32 powstat;
21 u32 cmdtstat;
22 u32 cmdtstaten;
[all …]
H A Dddr_rk3288.h11 u32 scfg;
12 u32 sctl;
13 u32 stat;
14 u32 intrstat;
15 u32 reserved0[12];
16 u32 mcmd;
17 u32 powctl;
18 u32 powstat;
19 u32 cmdtstat;
20 u32 tstaten;
[all …]
H A Dsdram_rk322x.h38 u32 scfg;
39 u32 sctl;
40 u32 stat;
41 u32 intrstat;
42 u32 reserved0[(0x40 - 0x10) / 4];
43 u32 mcmd;
44 u32 powctl;
45 u32 powstat;
46 u32 cmdtstat;
47 u32 cmdtstaten;
[all …]
H A Dgrf_rk3399.h11 u32 reserved[0x800];
12 u32 usb3_perf_con0;
13 u32 usb3_perf_con1;
14 u32 usb3_perf_con2;
15 u32 usb3_perf_rd_max_latency_num;
16 u32 usb3_perf_rd_latency_samp_num;
17 u32 usb3_perf_rd_latency_acc_num;
18 u32 usb3_perf_rd_axi_total_byte;
19 u32 usb3_perf_wr_axi_total_byte;
20 u32 usb3_perf_working_cnt;
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Domap_common.h20 u32 cm_clksel_core;
21 u32 cm_clksel_abe;
22 u32 cm_dll_ctrl;
23 u32 cm_clkmode_dpll_core;
24 u32 cm_idlest_dpll_core;
25 u32 cm_autoidle_dpll_core;
26 u32 cm_clksel_dpll_core;
27 u32 cm_div_m2_dpll_core;
28 u32 cm_div_m3_dpll_core;
29 u32 cm_div_h11_dpll_core;
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-socfpga/include/mach/
H A Dnic301.h11 u32 remap; /* 0x0 */
13 u32 _pad_0x4_0x8[1];
14 u32 l4main;
15 u32 l4sp;
16 u32 l4mp; /* 0x10 */
17 u32 l4osc1;
18 u32 l4spim;
19 u32 stm;
20 u32 lwhps2fpgaregs; /* 0x20 */
21 u32 _pad_0x24_0x28[1];
[all …]
H A Dsystem_manager_gen5.h19 u32 siliconid1; /* 0x00 */
20 u32 siliconid2;
21 u32 _pad_0x8_0xf[2];
22 u32 wddbg; /* 0x10 */
23 u32 bootinfo;
24 u32 hpsinfo;
25 u32 parityinj;
27 u32 fpgaintfgrp_gbl; /* 0x20 */
28 u32 fpgaintfgrp_indiv;
29 u32 fpgaintfgrp_module;
[all …]
/rk3399_rockchip-uboot/drivers/dma/
H A DMCD_tasks.c13 u32 MCD_varTab0[];
14 u32 MCD_varTab1[];
15 u32 MCD_varTab2[];
16 u32 MCD_varTab3[];
17 u32 MCD_varTab4[];
18 u32 MCD_varTab5[];
19 u32 MCD_varTab6[];
20 u32 MCD_varTab7[];
21 u32 MCD_varTab8[];
22 u32 MCD_varTab9[];
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rmobile/include/mach/
H A Dr8a7740.h49 u32 hpbctrl0;
50 u32 hpbctrl1;
51 u32 hpbctrl2;
52 u32 cccr;
53 u32 dummy0; /* 0x20 */
54 u32 hpbctrl4;
55 u32 hpbctrl5;
60 u32 frqcra;
61 u32 frqcrb;
62 u32 vclkcr1;
[all …]
H A Dsh73a0.h74 u32 hpbctrl0;
75 u32 hpbctrl1;
76 u32 hpbctrl2;
77 u32 cccr;
78 u32 dummy0; /* 0x20 */
79 u32 hpbctrl4;
80 u32 hpbctrl5;
81 u32 dummy1; /* 0x2C */
82 u32 hpbctrl6;
87 u32 mpsrc; /* 0x00 */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun8i_a23.h18 u32 clock;
19 u32 type;
20 u32 zq;
21 u32 odt_en;
23 u32 para1;
24 u32 para2;
25 u32 mr0;
26 u32 mr1;
27 u32 mr2;
28 u32 mr3;
[all …]
H A Ddram_sun6i.h18 u32 cr; /* 0x00 */
19 u32 ccr; /* 0x04 controller configuration register */
20 u32 dbgcr; /* 0x08 */
21 u32 dbgcr1; /* 0x0c */
22 u32 rmcr[8]; /* 0x10 */
23 u32 mmcr[16]; /* 0x30 */
24 u32 mbagcr[6]; /* 0x70 */
25 u32 maer; /* 0x88 */
27 u32 mdfscr; /* 0x100 */
28 u32 mdfsmer; /* 0x104 */
[all …]
H A Ddram_sun8i_a33.h16 u32 cr; /* 0x00 */
17 u32 ccr; /* 0x04 controller configuration register */
18 u32 dbgcr; /* 0x08 */
20 u32 mcr0_0; /* 0x10 */
21 u32 mcr1_0; /* 0x14 */
22 u32 mcr0_1; /* 0x18 */
23 u32 mcr1_1; /* 0x1c */
24 u32 mcr0_2; /* 0x20 */
25 u32 mcr1_2; /* 0x24 */
26 u32 mcr0_3; /* 0x28 */
[all …]
H A Ddisplay.h13 u32 enable; /* 0x000 */
14 u32 frame_ctrl; /* 0x004 */
15 u32 bypass; /* 0x008 */
16 u32 algorithm_sel; /* 0x00c */
17 u32 line_int_ctrl; /* 0x010 */
19 u32 ch0_addr; /* 0x020 */
20 u32 ch1_addr; /* 0x024 */
21 u32 ch2_addr; /* 0x028 */
22 u32 field_sequence; /* 0x02c */
23 u32 ch0_offset; /* 0x030 */
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx6/
H A Dmx6-ddr.h40 u32 mdctl;
41 u32 mdpdc;
42 u32 mdotc;
43 u32 mdcfg0;
44 u32 mdcfg1;
45 u32 mdcfg2;
46 u32 mdmisc;
47 u32 mdscr;
48 u32 mdref;
49 u32 res1[2];
[all …]
/rk3399_rockchip-uboot/include/
H A Dfsl_memac.h15 u32 res_0[2];
16 u32 command_config; /* Control and configuration register */
17 u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
18 u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
19 u32 maxfrm; /* Maximum frame length register */
20 u32 res_18[5];
21 u32 hashtable_ctrl; /* Hash table control register */
22 u32 res_30[4];
23 u32 ievent; /* Interrupt event register */
24 u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
[all …]
H A Dvsc9953.h198 u32 vlan_cfg;
199 u32 drop_cfg;
200 u32 qos_cfg;
201 u32 vcap_cfg;
202 u32 vcap_s1_key_cfg[3];
203 u32 vcap_s2_cfg;
204 u32 qos_pcp_dei_map_cfg[16];
205 u32 cpu_fwd_cfg;
206 u32 cpu_fwd_bpdu_cfg;
207 u32 cpu_fwd_garp_cfg;
[all …]
H A Dfsl_mmdc.h68 u32 mdctl;
69 u32 mdpdc;
70 u32 mdotc;
71 u32 mdcfg0;
72 u32 mdcfg1;
73 u32 mdcfg2;
74 u32 mdmisc;
75 u32 mdscr;
76 u32 mdref;
77 u32 res1[2];
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra20/
H A Dsdram_param.h30 u32 pllm_charge_pump_setup_control;
31 u32 pllm_loop_filter_setup_control;
32 u32 pllm_input_divider;
33 u32 pllm_feedback_divider;
34 u32 pllm_post_divider;
35 u32 pllm_stable_time;
36 u32 emc_clock_divider;
37 u32 emc_auto_cal_interval;
38 u32 emc_auto_cal_config;
39 u32 emc_auto_cal_wait;
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-hi6220/
H A Dhi6220_regs_alwayson.h14 u32 ctrl0; /*0x0*/
15 u32 ctrl1;
16 u32 ctrl2;
18 u32 unknown;
20 u32 stat0; /*0x10*/
21 u32 stat1;
22 u32 mcu_imctrl;
23 u32 mcu_imstat;
25 u32 unknown_1[9];
27 u32 secondary_int_en0; /*0x44*/
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h91 u32 porsr1; /* POR status 1 */
92 u32 porsr2; /* POR status 2 */
94 u32 gpporcr1; /* General-purpose POR configuration */
95 u32 gpporcr2;
96 u32 dcfg_fusesr; /* Fuse status register */
98 u32 devdisr; /* Device disable control */
99 u32 devdisr2; /* Device disable control 2 */
100 u32 devdisr3; /* Device disable control 3 */
101 u32 devdisr4; /* Device disable control 4 */
102 u32 devdisr5; /* Device disable control 5 */
[all …]

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