Lines Matching refs:u32
91 u32 porsr1; /* POR status 1 */
92 u32 porsr2; /* POR status 2 */
94 u32 gpporcr1; /* General-purpose POR configuration */
95 u32 gpporcr2;
96 u32 dcfg_fusesr; /* Fuse status register */
98 u32 devdisr; /* Device disable control */
99 u32 devdisr2; /* Device disable control 2 */
100 u32 devdisr3; /* Device disable control 3 */
101 u32 devdisr4; /* Device disable control 4 */
102 u32 devdisr5; /* Device disable control 5 */
104 u32 coredisru; /* uppper portion for support of 64 cores */
105 u32 coredisrl; /* lower portion for support of 64 cores */
107 u32 svr; /* System version */
109 u32 rstcr; /* Reset control */
110 u32 rstrqpblsr; /* Reset request preboot loader status */
112 u32 rstrqmr1; /* Reset request mask */
114 u32 rstrqsr1; /* Reset request status */
116 u32 rstrqwdtmrl; /* Reset request WDT mask */
118 u32 rstrqwdtsrl; /* Reset request WDT status */
120 u32 brrl; /* Boot release */
122 u32 rcwsr[16]; /* Reset control word status */
126 u32 scratchrw[4]; /* Scratch Read/Write */
128 u32 scratchw1r[4]; /* Scratch Read (Write once) */
130 u32 crstsr;
132 u32 sataliodnr;
134 u32 pamubypenr;
135 u32 dmacr1;
137 u32 tp_ityp[64]; /* Topology Initiator Type Register */
139 u32 upper;
140 u32 lower;
143 u32 ddrclkdr;
145 u32 ifcclkdr;
147 u32 sdhcpcr;
178 u32 dpslpcr;
179 u32 resv0[2];
180 u32 etsecclkdpslpcr;
181 u32 resv1[5];
182 u32 fuseovrdcr;
183 u32 pixclkcr;
184 u32 resv2[5];
185 u32 spimsicr;
186 u32 resv3[6];
187 u32 pex1pmwrcr;
188 u32 pex1pmrdsr;
189 u32 resv4[3];
190 u32 usb3prm1cr;
191 u32 usb4prm2cr;
192 u32 pex1rdmsgpldlsbsr;
193 u32 pex1rdmsgpldmsbsr;
194 u32 pex2rdmsgpldlsbsr;
195 u32 pex2rdmsgpldmsbsr;
196 u32 pex1rdmmsgrqsr;
197 u32 pex2rdmmsgrqsr;
198 u32 spimsiclrcr;
199 u32 pexmscportsr[2];
200 u32 pex2pmwrcr;
201 u32 resv5[24];
202 u32 mac1_streamid;
203 u32 mac2_streamid;
204 u32 mac3_streamid;
205 u32 pex1_streamid;
206 u32 pex2_streamid;
207 u32 dma_streamid;
208 u32 sata_streamid;
209 u32 usb3_streamid;
210 u32 qe_streamid;
211 u32 sdhc_streamid;
212 u32 adma_streamid;
213 u32 letechsftrstcr;
214 u32 core0_sft_rst;
215 u32 core1_sft_rst;
216 u32 resv6[1];
217 u32 usb_hi_addr;
218 u32 etsecclkadjcr;
219 u32 sai_clk;
220 u32 resv7[1];
221 u32 dcu_streamid;
222 u32 usb2_streamid;
223 u32 ftm_reset;
224 u32 altcbar;
225 u32 qspi_cfg;
226 u32 pmcintecr;
227 u32 pmcintlecr;
228 u32 pmcintsr;
229 u32 qos1;
230 u32 qos2;
231 u32 qos3;
232 u32 cci_cfg;
233 u32 endiancr;
234 u32 etsecdmamcr;
235 u32 usb3prm3cr;
236 u32 resv9[1];
237 u32 debug_streamid;
238 u32 resv10[5];
239 u32 snpcnfgcr;
240 u32 hrstcr;
241 u32 intpcr;
242 u32 resv12[20];
243 u32 scfgrevcr;
244 u32 coresrencr;
245 u32 pex2pmrdsr;
246 u32 eddrtqcfg;
247 u32 ddrc2cr;
248 u32 ddrc3cr;
249 u32 ddrc4cr;
250 u32 ddrgcr;
251 u32 resv13[120];
252 u32 qeioclkcr;
253 u32 etsecmcr;
254 u32 sdhciovserlcr;
255 u32 resv14[61];
256 u32 sparecr[8];
257 u32 resv15[248];
258 u32 core0sftrstsr;
259 u32 clusterpmcr;
265 u32 clkcncsr; /* core cluster n clock control status */
270 u32 pllcngsr;
274 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
276 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
278 u32 plldgsr; /* 0xc20 DDR PLL General Status */
284 u32 cntcr;
285 u32 cntsr;
286 u32 cntcv1;
287 u32 cntcv2;
288 u32 resv1[4];
289 u32 cntfid0;
290 u32 cntfid1;
291 u32 resv2[1002];
292 u32 counterid[12];
326 u32 rstctl; /* Reset Control Register */
328 u32 pllcr0; /* PLL Control Register 0 */
330 u32 pllcr1; /* PLL Control Register 1 */
331 u32 res_0c; /* 0x00c */
332 u32 pllcr3;
333 u32 pllcr4;
337 u32 srdstcalcr; /* 0x90 TX Calibration Control */
339 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
341 u32 srdsgr0; /* 0xb0 General Register 0 */
343 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
344 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
345 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
346 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
347 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
350 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
354 u32 srdspexeqcr;
355 u32 srdspexeqpcr[11];
357 u32 srdspexapcr;
359 u32 srdspexbpcr;
362 u32 gcr0; /* 0x800 General Control Register 0 */
363 u32 gcr1; /* 0x804 General Control Register 1 */
364 u32 gcr2; /* 0x808 General Control Register 2 */
365 u32 sscr0;
366 u32 recr0; /* 0x810 Receive Equalization Control */
367 u32 recr1;
368 u32 tecr0; /* 0x818 Transmit Equalization Control */
369 u32 sscr1;
370 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
372 u32 tcsr3;
385 u32 ctrl_ord; /* Control Override */
386 u32 spec_ctrl; /* Speculation Control */
387 u32 secure_access; /* Secure Access */
388 u32 status; /* Status */
389 u32 impr_err; /* Imprecise Error */
391 u32 pmcr; /* Performance Monitor Control */
393 u32 pid[8]; /* Peripheral ID */
394 u32 cid[4]; /* Component ID */
396 u32 snoop_ctrl; /* Snoop Control */
397 u32 sha_ord; /* Shareable Override */
399 u32 rc_qos_ord; /* read channel QoS Value Override */
400 u32 wc_qos_ord; /* read channel QoS Value Override */
402 u32 qos_ctrl; /* QoS Control */
403 u32 max_ot; /* Max OT */
405 u32 target_lat; /* Target Latency */
406 u32 latency_regu; /* Latency Regulation */
407 u32 qos_range; /* QoS Range */
411 u32 cycle_counter; /* Cycle counter */
412 u32 count_ctrl; /* Count Control */
413 u32 overflow_status; /* Overflow Flag Status */
416 u32 event_select; /* Event Select */
417 u32 event_count; /* Event Count */
418 u32 counter_ctrl; /* Counter Control */
419 u32 overflow_status; /* Overflow Flag Status */
427 u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
428 u32 pcfg; /* port config */
429 u32 ppcfg; /* port phy1 config */
430 u32 pp2c; /* port phy2 config */
431 u32 pp3c; /* port phy3 config */
432 u32 pp4c; /* port phy4 config */
433 u32 pp5c; /* port phy5 config */
434 u32 paxic; /* port AXI config */
435 u32 axicc; /* AXI cache control */
436 u32 axipc; /* AXI PROT control */
437 u32 ptc; /* port Trans Config */
438 u32 pts; /* port Trans Status */
439 u32 plc; /* port link config */
440 u32 plc1; /* port link config1 */
441 u32 plc2; /* port link config2 */
442 u32 pls; /* port link status */
443 u32 pls1; /* port link status1 */
444 u32 pcmdc; /* port CMD config */
445 u32 ppcs; /* port phy control status */
446 u32 pberr; /* port 0/1 BIST error */
447 u32 cmds; /* port 0/1 CMD status error */
470 u32 twaitsr;
472 u32 powmgtcsr;
474 u32 ippdexpcr0;
475 u32 ippdexpcr1;
477 u32 nfiqoutr;
479 u32 nirqoutr;
481 u32 dsimskr;
483 u32 clpcl10setr;