Merge git://git.denx.de/u-boot-fsl-qoriq

trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>

nxp: ls102xa: add registers definition for system sleep

This patch adds definitions of all the regesters necessary for
system sleep.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by:

nxp: ls102xa: add registers definition for system sleep

This patch adds definitions of all the regesters necessary for
system sleep.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

secure_boot: create function to determine boot mode

A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.co

secure_boot: create function to determine boot mode

A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

armv7/fsl-ls102xa: Workaround for DDR erratum A008514

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value

armv7/fsl-ls102xa: Workaround for DDR erratum A008514

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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arm: ls102xa: enable all the snoop signal for masters.

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for vari

arm: ls102xa: enable all the snoop signal for masters.

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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arm: ls102x: add get_svr and IS_SVR_REV helper

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit

This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking

arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit

This patch addresses a problem mentioned recently on this mailing list:
[1].

In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot. Debugging the problem reveals a stuck
interrupt 29 on the GIC.

It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value. This causes the timer compare to fire 344 seconds
after u-boot configures it. Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.

Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.

[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html

Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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Merge git://git.denx.de/u-boot

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

arm: ls1021a: Add sata support on qds and twr board

Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification

arm: ls1021a: Add sata support on qds and twr board

Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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arm: ls102xa: enable snooping for CAAM transactions

Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[S

arm: ls102xa: enable snooping for CAAM transactions

Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]

Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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ls102xa: etsec: Use proper settings for BE BDs

Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame d

ls102xa: etsec: Use proper settings for BE BDs

Replace the DMACTRL[LE] hack with recommended settings
for ETSECDMAMCR to get the same end effect - obtaining
big-endian buffer descriptors and frame data for eTSEC.
The reset / default value for ETSECDMAMCR is preserved,
excepting the BD and FR bits which are cleared to enable
the BE mode in accordance with the H/W specifications.

Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA"
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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Merge git://git.denx.de/u-boot-usb

include: usb: Move USB controller base address mapping

Move USB controller Base address mapping from ls102xa immap
to fsl xhci header. This is required to remove any warnings when
controller base ad

include: usb: Move USB controller base address mapping

Move USB controller Base address mapping from ls102xa immap
to fsl xhci header. This is required to remove any warnings when
controller base addresses are mapped for multiple platforms
in their respective files.

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>

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arch: arm: fsl: Add XHCI support for LS1021A

Add base register address information for USB
XHCI controller on LS1021A

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

arm/ls102xa: Add little-endian mode support for audio IPs

As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.

Si

arm/ls102xa: Add little-endian mode support for audio IPs

As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h

ccsr_ddr structure is already defined in fsl_immap.h. Remove
this duplicated define. Move fixed timing into ls1021atwr.h.

Signed-off-by: York Sun <

arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h

ccsr_ddr structure is already defined in fsl_immap.h. Remove
this duplicated define. Move fixed timing into ls1021atwr.h.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

arm/ls102xa:Add support of conditional workaround implementation as per SoC ver

For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.

arm/ls102xa:Add support of conditional workaround implementation as per SoC ver

For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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