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Searched refs:set_rate (Results 1 – 25 of 51) sorted by relevance

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/rk3399_rockchip-uboot/include/
H A Dgeneric-phy-dp.h74 u8 set_rate : 1; member
H A Dclk-uclass.h79 ulong (*set_rate)(struct clk *clk, ulong rate); member
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3399.c827 ulong clk_id, ulong set_rate) in rk3399_mmc_set_clk() argument
837 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3399_mmc_set_clk()
841 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3399_mmc_set_clk()
865 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); in rk3399_mmc_set_clk()
868 src_clk_div = DIV_ROUND_UP(OSC_HZ, set_rate); in rk3399_mmc_set_clk()
913 ulong set_rate) in rk3399_ddr_set_clk() argument
921 switch (set_rate) { in rk3399_ddr_set_clk()
951 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); in rk3399_ddr_set_clk()
955 return set_rate; in rk3399_ddr_set_clk()
1391 .set_rate = rk3399_clk_set_rate,
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H A Dclk_rk3368.c418 static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate) in rk3368_ddr_set_clk() argument
428 switch (set_rate) { in rk3368_ddr_set_clk()
439 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); in rk3368_ddr_set_clk()
443 return set_rate; in rk3368_ddr_set_clk()
448 static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate) in rk3368_gmac_set_clk() argument
458 ret = set_rate; in rk3368_gmac_set_clk()
474 div = DIV_ROUND_UP(pll_rate, set_rate) - 1; in rk3368_gmac_set_clk()
1257 .set_rate = rk3368_clk_set_rate,
H A Dclk_px30.c531 ulong set_rate) in px30_nandc_set_clk() argument
538 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_nandc_set_clk()
582 ulong clk_id, ulong set_rate) in px30_mmc_set_clk() argument
603 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in px30_mmc_set_clk()
607 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in px30_mmc_set_clk()
636 ulong clk_id, ulong set_rate) in px30_sfc_set_clk() argument
641 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in px30_sfc_set_clk()
1632 .set_rate = px30_clk_set_rate,
1889 .set_rate = px30_pmuclk_set_rate,
H A Dclk_rk1808.c222 ulong clk_id, ulong set_rate) in rk1808_mmc_set_clk() argument
247 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk1808_mmc_set_clk()
251 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk1808_mmc_set_clk()
280 ulong clk_id, ulong set_rate) in rk1808_sfc_set_clk() argument
285 src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate); in rk1808_sfc_set_clk()
1266 .set_rate = rk1808_clk_set_rate,
H A Dclk_rk3308.c336 static ulong rk3308_mmc_set_clk(struct clk *clk, ulong set_rate) in rk3308_mmc_set_clk() argument
343 debug("%s %ld %ld\n", __func__, clk->id, set_rate); in rk3308_mmc_set_clk()
359 src_clk_div = DIV_ROUND_UP(priv->vpll0_hz / 2, set_rate); in rk3308_mmc_set_clk()
363 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3308_mmc_set_clk()
1269 .set_rate = rk3308_clk_set_rate,
H A Dclk_rk3328.c345 ulong clk_id, ulong set_rate) in rk3328_mmc_set_clk() argument
365 src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, set_rate); in rk3328_mmc_set_clk()
369 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3328_mmc_set_clk()
1274 .set_rate = rk3328_clk_set_rate,
/rk3399_rockchip-uboot/drivers/clk/tegra/
H A Dtegra-car-clk.c86 .set_rate = tegra_car_clk_set_rate,
H A Dtegra186-clk.c87 .set_rate = tegra186_clk_set_rate,
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_sandbox.c71 .set_rate = sandbox_clk_set_rate,
H A Dclk_scmi.c92 .set_rate = scmi_clk_set_rate,
H A Dclk-uclass.c344 if (!ops->set_rate) in clk_set_rate()
347 return ops->set_rate(clk, rate); in clk_set_rate()
H A Dclk_pic32.c386 .set_rate = pic32_set_rate,
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c252 .set_rate = peri_clk_set_rate,
496 if (!c || !c->ops || !c->ops->set_rate) in clk_set_rate()
503 ret = c->ops->set_rate(c, rate); in clk_set_rate()
H A Dclk-core.h52 int (*set_rate) (struct clk *c, unsigned long rate); member
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c252 .set_rate = peri_clk_set_rate,
496 if (!c || !c->ops || !c->ops->set_rate) in clk_set_rate()
503 ret = c->ops->set_rate(c, rate); in clk_set_rate()
H A Dclk-core.h52 int (*set_rate)(struct clk *c, unsigned long rate); member
/rk3399_rockchip-uboot/drivers/clk/at91/
H A Dclk-generated.c147 .set_rate = generic_clk_set_rate,
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-naneng-edp.c248 if (dp->set_rate) { in rockchip_edp_phy_verify_config()
304 if (opts->dp.set_rate) { in rockchip_edp_phy_configure()
/rk3399_rockchip-uboot/drivers/clk/uniphier/
H A Dclk-uniphier-core.c127 .set_rate = uniphier_clk_set_rate,
/rk3399_rockchip-uboot/arch/arm/mach-snapdragon/
H A Dclock-apq8016.c246 .set_rate = msm_set_rate,
/rk3399_rockchip-uboot/drivers/video/
H A Dipu_common.c129 if (clk && clk->set_rate) in clk_set_rate()
130 clk->set_rate(clk, rate); in clk_set_rate()
400 .set_rate = ipu_pixel_clk_set_rate,
411 .set_rate = ipu_pixel_clk_set_rate,
H A Dipu.h49 int (*set_rate) (struct clk *, unsigned long); member
/rk3399_rockchip-uboot/drivers/clk/aspeed/
H A Dclk_ast2500.c424 .set_rate = ast2500_clk_set_rate,

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