1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2019 Cadence Design Systems Inc. 4 */ 5 6 #ifndef __PHY_DP_H_ 7 #define __PHY_DP_H_ 8 9 #define PHY_SUBMODE_DP 0 10 #define PHY_SUBMODE_EDP 1 11 12 /** 13 * struct phy_configure_opts_dp - DisplayPort PHY configuration set 14 * 15 * This structure is used to represent the configuration state of a 16 * DisplayPort phy. 17 */ 18 struct phy_configure_opts_dp { 19 /** 20 * @link_rate: 21 * 22 * Link Rate, in Mb/s, of the main link. 23 * 24 * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s 25 */ 26 unsigned int link_rate; 27 28 /** 29 * @lanes: 30 * 31 * Number of active, consecutive, data lanes, starting from 32 * lane 0, used for the transmissions on main link. 33 * 34 * Allowed values: 1, 2, 4 35 */ 36 unsigned int lanes; 37 38 /** 39 * @voltage: 40 * 41 * Voltage swing levels, as specified by DisplayPort specification, 42 * to be used by particular lanes. One value per lane. 43 * voltage[0] is for lane 0, voltage[1] is for lane 1, etc. 44 * 45 * Maximum value: 3 46 */ 47 unsigned int voltage[4]; 48 49 /** 50 * @pre: 51 * 52 * Pre-emphasis levels, as specified by DisplayPort specification, to be 53 * used by particular lanes. One value per lane. 54 * 55 * Maximum value: 3 56 */ 57 unsigned int pre[4]; 58 59 /** 60 * @ssc: 61 * 62 * Flag indicating, whether or not to enable spread-spectrum clocking. 63 * 64 */ 65 u8 ssc : 1; 66 67 /** 68 * @set_rate: 69 * 70 * Flag indicating, whether or not reconfigure link rate and SSC to 71 * requested values. 72 * 73 */ 74 u8 set_rate : 1; 75 76 /** 77 * @set_lanes: 78 * 79 * Flag indicating, whether or not reconfigure lane count to 80 * requested value. 81 * 82 */ 83 u8 set_lanes : 1; 84 85 /** 86 * @set_voltages: 87 * 88 * Flag indicating, whether or not reconfigure voltage swing 89 * and pre-emphasis to requested values. Only lanes specified 90 * by "lanes" parameter will be affected. 91 * 92 */ 93 u8 set_voltages : 1; 94 }; 95 96 #endif /* __PHY_DP_H_ */ 97