1672d3078SWyon Bi /* SPDX-License-Identifier: GPL-2.0 */ 2672d3078SWyon Bi /* 3672d3078SWyon Bi * Copyright (C) 2019 Cadence Design Systems Inc. 4672d3078SWyon Bi */ 5672d3078SWyon Bi 6672d3078SWyon Bi #ifndef __PHY_DP_H_ 7672d3078SWyon Bi #define __PHY_DP_H_ 8672d3078SWyon Bi 9*2192a6fcSDamon Ding #define PHY_SUBMODE_DP 0 10*2192a6fcSDamon Ding #define PHY_SUBMODE_EDP 1 11*2192a6fcSDamon Ding 12672d3078SWyon Bi /** 13672d3078SWyon Bi * struct phy_configure_opts_dp - DisplayPort PHY configuration set 14672d3078SWyon Bi * 15672d3078SWyon Bi * This structure is used to represent the configuration state of a 16672d3078SWyon Bi * DisplayPort phy. 17672d3078SWyon Bi */ 18672d3078SWyon Bi struct phy_configure_opts_dp { 19672d3078SWyon Bi /** 20672d3078SWyon Bi * @link_rate: 21672d3078SWyon Bi * 22672d3078SWyon Bi * Link Rate, in Mb/s, of the main link. 23672d3078SWyon Bi * 24672d3078SWyon Bi * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s 25672d3078SWyon Bi */ 26672d3078SWyon Bi unsigned int link_rate; 27672d3078SWyon Bi 28672d3078SWyon Bi /** 29672d3078SWyon Bi * @lanes: 30672d3078SWyon Bi * 31672d3078SWyon Bi * Number of active, consecutive, data lanes, starting from 32672d3078SWyon Bi * lane 0, used for the transmissions on main link. 33672d3078SWyon Bi * 34672d3078SWyon Bi * Allowed values: 1, 2, 4 35672d3078SWyon Bi */ 36672d3078SWyon Bi unsigned int lanes; 37672d3078SWyon Bi 38672d3078SWyon Bi /** 39672d3078SWyon Bi * @voltage: 40672d3078SWyon Bi * 41672d3078SWyon Bi * Voltage swing levels, as specified by DisplayPort specification, 42672d3078SWyon Bi * to be used by particular lanes. One value per lane. 43672d3078SWyon Bi * voltage[0] is for lane 0, voltage[1] is for lane 1, etc. 44672d3078SWyon Bi * 45672d3078SWyon Bi * Maximum value: 3 46672d3078SWyon Bi */ 47672d3078SWyon Bi unsigned int voltage[4]; 48672d3078SWyon Bi 49672d3078SWyon Bi /** 50672d3078SWyon Bi * @pre: 51672d3078SWyon Bi * 52672d3078SWyon Bi * Pre-emphasis levels, as specified by DisplayPort specification, to be 53672d3078SWyon Bi * used by particular lanes. One value per lane. 54672d3078SWyon Bi * 55672d3078SWyon Bi * Maximum value: 3 56672d3078SWyon Bi */ 57672d3078SWyon Bi unsigned int pre[4]; 58672d3078SWyon Bi 59672d3078SWyon Bi /** 60672d3078SWyon Bi * @ssc: 61672d3078SWyon Bi * 62672d3078SWyon Bi * Flag indicating, whether or not to enable spread-spectrum clocking. 63672d3078SWyon Bi * 64672d3078SWyon Bi */ 65672d3078SWyon Bi u8 ssc : 1; 66672d3078SWyon Bi 67672d3078SWyon Bi /** 68672d3078SWyon Bi * @set_rate: 69672d3078SWyon Bi * 70672d3078SWyon Bi * Flag indicating, whether or not reconfigure link rate and SSC to 71672d3078SWyon Bi * requested values. 72672d3078SWyon Bi * 73672d3078SWyon Bi */ 74672d3078SWyon Bi u8 set_rate : 1; 75672d3078SWyon Bi 76672d3078SWyon Bi /** 77672d3078SWyon Bi * @set_lanes: 78672d3078SWyon Bi * 79672d3078SWyon Bi * Flag indicating, whether or not reconfigure lane count to 80672d3078SWyon Bi * requested value. 81672d3078SWyon Bi * 82672d3078SWyon Bi */ 83672d3078SWyon Bi u8 set_lanes : 1; 84672d3078SWyon Bi 85672d3078SWyon Bi /** 86672d3078SWyon Bi * @set_voltages: 87672d3078SWyon Bi * 88672d3078SWyon Bi * Flag indicating, whether or not reconfigure voltage swing 89672d3078SWyon Bi * and pre-emphasis to requested values. Only lanes specified 90672d3078SWyon Bi * by "lanes" parameter will be affected. 91672d3078SWyon Bi * 92672d3078SWyon Bi */ 93672d3078SWyon Bi u8 set_voltages : 1; 94672d3078SWyon Bi }; 95672d3078SWyon Bi 96672d3078SWyon Bi #endif /* __PHY_DP_H_ */ 97