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Searched refs:cs (Results 1 – 25 of 374) sorted by relevance

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/rk3399_rockchip-uboot/drivers/rkflash/
H A Dflash.c47 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
51 nandc_flash_reset(cs); in flash_read_id_raw()
52 nandc_flash_cs(cs); in flash_read_id_raw()
53 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
54 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
57 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
58 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
59 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
60 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
61 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
[all …]
/rk3399_rockchip-uboot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c79 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
80 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
81 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
82 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
83 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
84 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
85 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
86 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
87 .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG,
111 .cs[0].bnds = CONFIG_SYS_DDR2_CS0_BNDS,
[all …]
/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c47 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
107 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
108 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
116 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
124 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
128 cs, pup); in ddr3_write_leveling_hw()
129 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
[all …]
H A Dddr3_read_leveling.c45 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
49 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
98 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
99 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
107 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
122 cs, pup); in ddr3_read_leveling_hw()
[all …]
H A Dddr3_spd.c582 u32 cs, cl, cs_num, cs_ena; local
662 for (cs = 0; cs < MAX_CS; cs += 2) {
663 if (((1 << cs) & DIMM_CS_BITMAP) &&
664 !(cs_ena & (1 << cs))) {
666 cs_ena |= (0x1 << cs);
668 cs_ena |= (0x3 << cs);
670 cs_ena |= (0x7 << cs);
672 cs_ena |= (0xF << cs);
897 for (cs = 0; cs < MAX_CS; cs++) {
898 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
[all …]
H A Dddr3_dfs.c118 u32 cs = 0; in ddr3_dfs_high_2_low() local
196 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
197 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
199 (cs << MR_CS_ADDR_OFFS)); in ddr3_dfs_high_2_low()
202 (cs << MR_CS_ADDR_OFFS), reg); in ddr3_dfs_high_2_low()
442 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
443 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_high_2_low()
444 reg &= ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_dfs_high_2_low()
468 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()
469 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
[all …]
H A Dddr3_dqs.c68 int ddr3_find_adll_limits(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, int is_tx);
71 static int ddr3_center_calc(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
73 int ddr3_special_pattern_i_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
75 int ddr3_special_pattern_ii_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
77 int ddr3_set_dqs_centralization_results(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
133 u32 cs, ecc, reg; in ddr3_dqs_centralization_rx() local
151 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_rx()
152 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_rx()
154 (u32) cs, 1); in ddr3_dqs_centralization_rx()
172 status = ddr3_find_adll_limits(dram_info, cs, in ddr3_dqs_centralization_rx()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c41 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
69 u32 get_sdr_cs_size(u32 cs) in get_sdr_cs_size() argument
74 size = readl(&sdrc_base->cs[cs].mcfg) >> 8; in get_sdr_cs_size()
84 u32 get_sdr_cs_offset(u32 cs) in get_sdr_cs_offset() argument
88 if (!cs) in get_sdr_cs_offset()
102 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, in write_sdrc_timings() argument
106 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
109 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); in write_sdrc_timings()
110 writel(CMD_NOP, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
111 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
[all …]
H A Dspl_id_nand.c39 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
40 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
41 while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) in identify_nand_chip()
47 writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
50 writeb(0x0, &gpmc_cfg->cs[0].nand_adr); in identify_nand_chip()
53 *mfr = readb(&gpmc_cfg->cs[0].nand_dat); in identify_nand_chip()
54 *id = readb(&gpmc_cfg->cs[0].nand_dat); in identify_nand_chip()
/rk3399_rockchip-uboot/board/tqc/tqm834x/
H A Dtqm834x.c45 static long int get_ddr_bank_size(short cs, long *base);
46 static void set_cs_bounds(short cs, ulong base, ulong size);
47 static void set_cs_config(short cs, long config);
73 int cs; in dram_init() local
80 for(cs = 0; cs < 4; ++cs) { in dram_init()
81 set_cs_bounds(cs, in dram_init()
82 CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), in dram_init()
85 set_cs_config(cs, INITIAL_CS_CONFIG); in dram_init()
102 for(cs = 0; cs < 4; ++cs) { in dram_init()
103 debug("\nDetecting Bank%d\n", cs); in dram_init()
[all …]
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c198 u32 reg, cs; in ddr3_restore_and_set_final_windows() local
200 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
201 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
202 reg |= (cs << 2); in ddr3_restore_and_set_final_windows()
214 u32 reg, tmp_count, cs, ui; in ddr3_save_and_set_training_windows() local
245 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_save_and_set_training_windows()
246 if (cs_ena & (1 << cs)) { in ddr3_save_and_set_training_windows()
247 switch (cs) { in ddr3_save_and_set_training_windows()
521 u32 cs; in ddr3_get_cs_num_from_reg() local
523 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_get_cs_num_from_reg()
[all …]
/rk3399_rockchip-uboot/test/dm/
H A Dspi.c25 const int busnum = 0, cs = 0, mode = 0, speed = 1000000, cs_b = 1; in dm_test_spi_find() local
37 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
46 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
50 ut_asserteq(-ENODEV, spi_find_bus_and_cs(busnum, cs, &bus, &dev)); in dm_test_spi_find()
51 ut_asserteq(-ENODEV, spi_get_bus_and_cs(busnum, cs, speed, mode, in dm_test_spi_find()
60 ut_asserteq(-ENODEV, spi_find_bus_and_cs(busnum, cs, &bus, &dev)); in dm_test_spi_find()
61 ut_asserteq(-ENOENT, spi_get_bus_and_cs(busnum, cs, speed, mode, in dm_test_spi_find()
64 sandbox_sf_unbind_emul(state_get_current(), busnum, cs); in dm_test_spi_find()
65 ut_assertok(spi_cs_info(bus, cs, &info)); in dm_test_spi_find()
69 ut_assertok(sandbox_sf_bind_emul(state, busnum, cs, bus, node, in dm_test_spi_find()
[all …]
/rk3399_rockchip-uboot/drivers/video/
H A Dhitachi_tx18d42vm_lcd.c19 static void lcd_panel_spi_write(int cs, int clk, int mosi, in lcd_panel_spi_write() argument
24 gpio_direction_output(cs, 0); in lcd_panel_spi_write()
33 gpio_direction_output(cs, 1); in lcd_panel_spi_write()
49 int i, cs, clk, mosi, ret = 0; in hitachi_tx18d42vm_init() local
51 cs = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); in hitachi_tx18d42vm_init()
55 if (cs == -1 || clk == -1 || mosi == 1) { in hitachi_tx18d42vm_init()
60 if (gpio_request(cs, "tx18d42vm-spi-cs") != 0 || in hitachi_tx18d42vm_init()
69 lcd_panel_spi_write(cs, clk, mosi, init_data[i], 16); in hitachi_tx18d42vm_init()
73 lcd_panel_spi_write(cs, clk, mosi, 0x00ad, 16); /* display on */ in hitachi_tx18d42vm_init()
78 gpio_free(cs); in hitachi_tx18d42vm_init()
/rk3399_rockchip-uboot/drivers/memory/
H A Dti-aemif.c16 #define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \ argument
17 + (cs * 4))
38 static void aemif_configure(int cs, struct aemif_config *cfg) in aemif_configure() argument
44 tmp |= (1 << cs); in aemif_configure()
49 tmp |= (1 << cs); in aemif_configure()
53 tmp = __raw_readl(AEMIF_CONFIG(cs)); in aemif_configure()
66 __raw_writel(tmp, AEMIF_CONFIG(cs)); in aemif_configure()
71 int cs; in aemif_init() local
78 for (cs = 0; cs < num_cs; cs++) in aemif_init()
79 aemif_configure(cs, config + cs); in aemif_init()
/rk3399_rockchip-uboot/arch/arm/mach-omap2/
H A Dmem-common.c43 u32 mem_ok(u32 cs) in mem_ok() argument
48 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); in mem_ok()
64 void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, in enable_gpmc_cs_config() argument
67 writel(0, &cs->config7); in enable_gpmc_cs_config()
70 writel(gpmc_config[0], &cs->config1); in enable_gpmc_cs_config()
71 writel(gpmc_config[1], &cs->config2); in enable_gpmc_cs_config()
72 writel(gpmc_config[2], &cs->config3); in enable_gpmc_cs_config()
73 writel(gpmc_config[3], &cs->config4); in enable_gpmc_cs_config()
74 writel(gpmc_config[4], &cs->config5); in enable_gpmc_cs_config()
75 writel(gpmc_config[5], &cs->config6); in enable_gpmc_cs_config()
[all …]
/rk3399_rockchip-uboot/cmd/
H A Dmmc_spi.c35 uint cs = CONFIG_MMC_SPI_CS; in do_mmc_spi() local
44 cs = simple_strtoul(argv[1], &endp, 0); in do_mmc_spi()
50 bus = cs; in do_mmc_spi()
51 cs = simple_strtoul(endp + 1, &endp, 0); in do_mmc_spi()
65 if (!spi_cs_is_valid(bus, cs)) { in do_mmc_spi()
66 printf("Invalid SPI bus %u cs %u\n", bus, cs); in do_mmc_spi()
70 mmc = mmc_spi_init(bus, cs, speed, mode); in do_mmc_spi()
76 mmc->block_dev.devnum, bus, cs, speed, mode); in do_mmc_spi()
H A Dspi.c37 static unsigned int cs; variable
43 static int do_spi_xfer(int bus, int cs) in do_spi_xfer() argument
52 snprintf(name, sizeof(name), "generic_%d:%d", bus, cs); in do_spi_xfer()
56 ret = spi_get_bus_and_cs(bus, cs, 1000000, mode, "spi_generic_drv", in do_spi_xfer()
61 slave = spi_setup_slave(bus, cs, 1000000, mode); in do_spi_xfer()
63 printf("Invalid device %d:%d\n", bus, cs); in do_spi_xfer()
124 cs = simple_strtoul(cp+1, &cp, 10); in do_spi()
126 cs = bus; in do_spi()
159 if (do_spi_xfer(bus, cs)) in do_spi()
/rk3399_rockchip-uboot/drivers/spi/
H A Domap3_spi.c116 unsigned int cs; member
125 writel(val, &priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
127 readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
132 writel(enable, &priv->regs->channel[priv->cs].chctrl); in omap3_spi_set_enable()
134 readl(&priv->regs->channel[priv->cs].chctrl); in omap3_spi_set_enable()
143 chconf = readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write()
157 while (!(readl(&priv->regs->channel[priv->cs].chstat) & in omap3_spi_write()
161 readl(&priv->regs->channel[priv->cs].chstat)); in omap3_spi_write()
166 unsigned int *tx = &priv->regs->channel[priv->cs].tx; in omap3_spi_write()
176 while ((readl(&priv->regs->channel[priv->cs].chstat) & in omap3_spi_write()
[all …]
H A Dsandbox_spi.c32 unsigned long *cs) in sandbox_spi_parse_spec() argument
40 *cs = simple_strtoul(endp + 1, &endp, 0); in sandbox_spi_parse_spec()
41 if (*endp != ':' || *cs >= CONFIG_SANDBOX_SPI_MAX_CS) in sandbox_spi_parse_spec()
63 uint busnum, cs; in sandbox_spi_xfer() local
76 cs = spi_chip_select(slave); in sandbox_spi_xfer()
78 cs >= CONFIG_SANDBOX_SPI_MAX_CS) { in sandbox_spi_xfer()
80 busnum, cs); in sandbox_spi_xfer()
86 __func__, busnum, cs, ret); in sandbox_spi_xfer()
117 static int sandbox_cs_info(struct udevice *bus, uint cs, in sandbox_cs_info() argument
121 if (cs >= 1) in sandbox_cs_info()
H A Dfsl_espi.c66 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, in spi_setup_slave() argument
75 if (!spi_cs_is_valid(bus, cs)) in spi_setup_slave()
78 fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); in spi_setup_slave()
132 unsigned int cs = slave->cs; in spi_claim_bus() local
137 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); in spi_claim_bus()
150 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & in spi_claim_bus()
156 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
161 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
164 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
168 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
[all …]
/rk3399_rockchip-uboot/board/atmel/at91sam9261ek/
H A Dat91sam9261ek.c51 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
54 &smc->cs[3].pulse); in at91sam9261ek_nand_hw_init()
56 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
60 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
63 &smc->cs[3].pulse); in at91sam9261ek_nand_hw_init()
65 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
75 &smc->cs[3].mode); in at91sam9261ek_nand_hw_init()
99 &smc->cs[2].setup); in at91sam9261ek_dm9000_hw_init()
102 &smc->cs[2].pulse); in at91sam9261ek_dm9000_hw_init()
104 &smc->cs[2].cycle); in at91sam9261ek_dm9000_hw_init()
[all …]
/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c75 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
76 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
79 csn_bnds_backup = regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
80 csn_bnds_t = (unsigned int *) &regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
82 *csn_bnds_t = regs->cs[i].bnds + 0x01000000; in fsl_ddr_set_memctl_regs()
84 *csn_bnds_t = regs->cs[i].bnds + 0x01000100; in fsl_ddr_set_memctl_regs()
87 csn, csn_bnds_backup, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
94 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
95 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
96 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc85xx_ddr_gen1.c29 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
30 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
33 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
37 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
41 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
H A Darm_ddr_gen3.c71 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
72 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
73 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
76 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
77 ddr_out32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
78 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
81 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
82 ddr_out32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
83 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
86 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
/rk3399_rockchip-uboot/include/
H A Dspi.h76 unsigned int cs; member
115 unsigned int cs;
155 unsigned int cs);
168 #define spi_alloc_slave(_struct, bus, cs) \ argument
170 sizeof(_struct), bus, cs)
181 #define spi_alloc_slave_base(bus, cs) \ argument
182 spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs)
200 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
305 int spi_cs_is_valid(unsigned int bus, unsigned int cs);
487 int (*cs_info)(struct udevice *bus, uint cs, struct spi_cs_info *info);
[all …]

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