Lines Matching refs:cs
45 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
49 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
98 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
99 if (dram_info->cs_ena & (1 << cs)) { in ddr3_read_leveling_hw()
107 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
122 cs, pup); in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
129 (u32) cs, 1); in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
182 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
203 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_sw()
204 DEBUG_RL_C("DDR3 - Read Leveling - CS - ", (u32) cs, 1); in ddr3_read_leveling_sw()
222 (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
224 (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
230 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
234 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
238 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_sw()
245 ddr3_read_leveling_single_cs_rl_mode(cs, freq, in ddr3_read_leveling_sw()
253 ddr3_read_leveling_single_cs_window_mode(cs, freq, in ddr3_read_leveling_sw()
263 DEBUG_RL_C("DDR3 - Read Leveling - Results for CS - ", (u32) cs, in ddr3_read_leveling_sw()
272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw()
291 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
292 delay = dram_info->rl_val[cs][pup][D]; in ddr3_read_leveling_sw()
293 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, in ddr3_read_leveling_sw()
336 static void overrun(u32 cs, MV_DRAM_INFO *info, u32 pup, u32 locked_pups, in overrun() argument
348 if (info->rl_val[cs][idx][S] == RL_UNLOCK_STATE) { in overrun()
351 if (info->rl_val[cs][idx][C] < RL_RETRY_COUNT) { in overrun()
354 info->rl_val[cs][idx][C]++; in overrun()
357 if (info->rl_val[cs][idx][C] == RL_RETRY_COUNT) { in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
363 info->rl_val[cs][idx][S] = RL_FINAL_STATE; in overrun()
400 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq, in ddr3_read_leveling_single_cs_rl_mode() argument
410 DEBUG_RL_FULL_C("DDR3 - Read Leveling - Single CS - ", (u32) cs, 1); in ddr3_read_leveling_single_cs_rl_mode()
423 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_rl_mode()
443 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_rl_mode()
457 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_rl_mode()
471 overrun(cs, dram_info, pup, locked_pups, in ddr3_read_leveling_single_cs_rl_mode()
579 if (dram_info->rl_val[cs][idx][S] in ddr3_read_leveling_single_cs_rl_mode()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
620 * cs)); in ddr3_read_leveling_single_cs_rl_mode()
623 cs)); in ddr3_read_leveling_single_cs_rl_mode()
669 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
671 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
681 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_rl_mode()
682 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_rl_mode()
690 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
691 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
725 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
726 reg |= ((rd_sample_delay + add) << (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_rl_mode()
730 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_rl_mode()
732 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_rl_mode()
733 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_rl_mode()
752 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq, in ddr3_read_leveling_single_cs_window_mode() argument
762 DEBUG_RL_FULL_C("DDR3 - Read Leveling - Single CS - ", (u32) cs, 1); in ddr3_read_leveling_single_cs_window_mode()
777 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_window_mode()
797 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_window_mode()
811 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_window_mode()
834 if (dram_info->rl_val[cs][idx][S] == RL_WINDOW_STATE) { in ddr3_read_leveling_single_cs_window_mode()
847 dram_info->rl_val[cs][idx][DE] = delay; in ddr3_read_leveling_single_cs_window_mode()
848 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode()
850 dram_info->rl_val[cs][idx][S]++; in ddr3_read_leveling_single_cs_window_mode()
857 } else if (dram_info->rl_val[cs][idx][S] == in ddr3_read_leveling_single_cs_window_mode()
864 if (dram_info->rl_val[cs][idx][C] < in ddr3_read_leveling_single_cs_window_mode()
870 dram_info->rl_val[cs][idx][C]++; in ddr3_read_leveling_single_cs_window_mode()
873 if (dram_info->rl_val[cs][idx][C] == in ddr3_read_leveling_single_cs_window_mode()
875 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
876 dram_info->rl_val[cs][idx][DS] = in ddr3_read_leveling_single_cs_window_mode()
878 dram_info->rl_val[cs][idx][PS] = in ddr3_read_leveling_single_cs_window_mode()
880 dram_info->rl_val[cs][idx][S]++; /* Go to Window State */ in ddr3_read_leveling_single_cs_window_mode()
1025 * cs)); in ddr3_read_leveling_single_cs_window_mode()
1028 cs)); in ddr3_read_leveling_single_cs_window_mode()
1071 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1073 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1084 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_window_mode()
1085 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
1096 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1); in ddr3_read_leveling_single_cs_window_mode()
1098 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DS], 2); in ddr3_read_leveling_single_cs_window_mode()
1100 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode()
1102 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DE], 2); in ddr3_read_leveling_single_cs_window_mode()
1111 if (dram_info->rl_val[cs][idx][PS] == 4) in ddr3_read_leveling_single_cs_window_mode()
1112 dram_info->rl_val[cs][idx][PS] = 1; in ddr3_read_leveling_single_cs_window_mode()
1113 if (dram_info->rl_val[cs][idx][PE] == 4) in ddr3_read_leveling_single_cs_window_mode()
1114 dram_info->rl_val[cs][idx][PE] = 1; in ddr3_read_leveling_single_cs_window_mode()
1116 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1117 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1118 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1119 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1129 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1130 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY_INV; in ddr3_read_leveling_single_cs_window_mode()
1133 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1134 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1135 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1136 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1145 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1149 if (dram_info->rl_val[cs][idx][PS] > 1) in ddr3_read_leveling_single_cs_window_mode()
1150 dram_info->rl_val[cs][idx][PS] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1151 if (dram_info->rl_val[cs][idx][PE] > 1) in ddr3_read_leveling_single_cs_window_mode()
1152 dram_info->rl_val[cs][idx][PE] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1155 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1157 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1158 dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1169 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1199 (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1201 ((rd_sample_delay + add) << (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_read_leveling_single_cs_window_mode()
1205 for (cs = 0; cs < dram_info->num_cs; cs++) { in ddr3_read_leveling_single_cs_window_mode()
1207 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_window_mode()
1208 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_window_mode()