Lines Matching refs:cs
582 u32 cs, cl, cs_num, cs_ena; local
662 for (cs = 0; cs < MAX_CS; cs += 2) {
663 if (((1 << cs) & DIMM_CS_BITMAP) &&
664 !(cs_ena & (1 << cs))) {
666 cs_ena |= (0x1 << cs);
668 cs_ena |= (0x3 << cs);
670 cs_ena |= (0x7 << cs);
672 cs_ena |= (0xF << cs);
897 for (cs = 0; cs < MAX_CS; cs++) {
898 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
907 (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs)));
911 (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs)));
913 (REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS + cs));
921 for (cs = 0; cs < MAX_CS; cs++) {
922 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
929 reg |= (1 << (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs));
937 for (cs = 0; cs < MAX_CS; cs++) {
938 if (cs_ena & (1 << cs))
939 reg &= ~(1 << (cs + REG_SDRAM_OPERATION_CS_OFFS));
1014 for (cs = 0; cs < MAX_CS; cs++) {
1015 if ((1 << cs) & DIMM_CS_BITMAP) {
1016 if ((1 << cs) & cs_ena) {
1023 reg_write(REG_CS_SIZE_SCRATCH_ADDR + (cs * 0x8),
1026 reg_write(REG_CS_SIZE_SCRATCH_ADDR + (cs * 0x8), 0);
1037 for (cs = 0; cs < MAX_CS; cs++) {
1038 if (cs_ena & (1 << cs))
1039 reg |= (cl << (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs));
1048 for (cs = 0; cs < MAX_CS; cs++) {
1049 if (cs_ena & (1 << cs)) {
1051 (REG_READ_DATA_READY_DELAYS_OFFS * cs));
1063 for (cs = 0; cs < MAX_CS; cs++) {
1064 if (cs_ena & (1 << cs)) {
1066 (cs << MR_CS_ADDR_OFFS), reg);
1075 for (cs = 0; cs < MAX_CS; cs++) {
1076 if (cs_ena & (1 << cs)) {
1077 reg |= odt_static[cs_ena][cs];
1079 (cs << MR_CS_ADDR_OFFS), reg);
1112 for (cs = 0; cs < MAX_CS; cs++) {
1113 if (cs_ena & (1 << cs)) {
1115 reg |= odt_dynamic[cs_ena][cs];
1117 (cs << MR_CS_ADDR_OFFS), reg);
1123 for (cs = 0; cs < MAX_CS; cs++) {
1124 if (cs_ena & (1 << cs)) {
1126 (cs << MR_CS_ADDR_OFFS), reg);
1150 for (cs = 0; cs < MAX_CS; cs++) {
1151 if (cs_ena & (1 << cs) & DIMM_CS_BITMAP) {
1159 (cs == 1 || cs == 3) &&
1161 reg |= (1 << (REG_DDR3_RANK_CTRL_MIRROR_OFFS + cs));
1163 cs, 1);