Lines Matching refs:cs
47 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
107 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()
108 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw()
116 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
124 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw()
128 cs, pup); in ddr3_write_leveling_hw()
129 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
136 DEBUG_WL_D((u32) cs, 1); in ddr3_write_leveling_hw()
148 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
152 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw()
187 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
229 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
230 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
307 DEBUG_WL_D((u32) cs, 1); in ddr3_wl_supplement()
339 dram_info->wl_val[cs] in ddr3_wl_supplement()
346 [cs] in ddr3_wl_supplement()
350 dram_info->wl_val[cs] in ddr3_wl_supplement()
355 [cs][pup_num] in ddr3_wl_supplement()
359 (PUP_WL_MODE, cs, in ddr3_wl_supplement()
367 [cs][pup_num] in ddr3_wl_supplement()
371 [cs][pup_num] in ddr3_wl_supplement()
383 dram_info->wl_val[cs] in ddr3_wl_supplement()
386 dram_info->wl_val[cs] in ddr3_wl_supplement()
390 (PUP_WL_MODE, cs, in ddr3_wl_supplement()
410 sum += dram_info->wl_val[cs][pup][S]; in ddr3_wl_supplement()
413 sum += dram_info->wl_val[cs][ECC_PUP][S]; in ddr3_wl_supplement()
418 (u32) cs, 1); in ddr3_wl_supplement()
431 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()
432 if (dram_info->cs_ena & (1 << cs)) { in ddr3_wl_supplement()
437 reg = ddr3_read_pup_reg(PUP_WL_MODE, cs, pup); in ddr3_wl_supplement()
475 u32 reg, phase, delay, cs, pup, pup_num; in ddr3_write_leveling_hw_reg_dimm() local
530 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
531 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
539 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
545 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw_reg_dimm()
546 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw_reg_dimm()
553 cs, pup, 0, in ddr3_write_leveling_hw_reg_dimm()
555 dram_info->wl_val[cs][pup][P] = in ddr3_write_leveling_hw_reg_dimm()
557 dram_info->wl_val[cs][pup][D] = in ddr3_write_leveling_hw_reg_dimm()
560 dram_info->wl_val[cs][pup][S] = in ddr3_write_leveling_hw_reg_dimm()
564 cs, pup); in ddr3_write_leveling_hw_reg_dimm()
565 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw_reg_dimm()
574 DEBUG_WL_D((u32) cs, 1); in ddr3_write_leveling_hw_reg_dimm()
584 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
588 dram_info->wl_val[cs][pup] in ddr3_write_leveling_hw_reg_dimm()
619 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()
620 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_hw_reg_dimm()
627 ddr3_write_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
660 u32 reg, cs, cnt, pup, max_pup_num; in ddr3_write_leveling_sw() local
679 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
680 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
683 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
690 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
722 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
723 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
725 (u32) cs, 1); in ddr3_write_leveling_sw()
732 + cs)); in ddr3_write_leveling_sw()
750 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
757 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
769 ddr3_write_leveling_single_cs(cs, freq, ratio_2to1, in ddr3_write_leveling_sw()
770 (u32 *)(res + cs), in ddr3_write_leveling_sw()
773 (u32) cs, 1); in ddr3_write_leveling_sw()
775 if (((res[cs] >> pup) & 0x1) == 0) { in ddr3_write_leveling_sw()
793 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Finished Cs - ", (u32) cs, in ddr3_write_leveling_sw()
796 (u32) res[cs], 3); in ddr3_write_leveling_sw()
810 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
837 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()
838 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw()
842 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw()
848 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw()
885 u32 reg, cs, cnt, pup; in ddr3_write_leveling_sw_reg_dimm() local
914 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
915 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
918 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw_reg_dimm()
925 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
955 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
956 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
958 (u32) cs, 1); in ddr3_write_leveling_sw_reg_dimm()
966 + cs)); in ddr3_write_leveling_sw_reg_dimm()
987 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw_reg_dimm()
998 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
1010 ddr3_write_leveling_single_cs(cs, freq, ratio_2to1, in ddr3_write_leveling_sw_reg_dimm()
1011 (u32 *)(res + cs), in ddr3_write_leveling_sw_reg_dimm()
1014 (u32) cs, 1); in ddr3_write_leveling_sw_reg_dimm()
1028 DEBUG_WL_FULL_C("DDR3 - Write Leveling - Finished Cs - ", (u32) cs, in ddr3_write_leveling_sw_reg_dimm()
1031 (u32) res[cs], 3); in ddr3_write_leveling_sw_reg_dimm()
1042 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
1069 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw_reg_dimm()
1070 if (dram_info->cs_ena & (1 << cs)) { in ddr3_write_leveling_sw_reg_dimm()
1074 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_write_leveling_sw_reg_dimm()
1080 ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_write_leveling_sw_reg_dimm()
1125 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1, in ddr3_write_leveling_single_cs() argument
1136 (u32) cs, 1); in ddr3_write_leveling_single_cs()
1167 reg |= (REG_SDRAM_ODT_CTRL_HIGH_OVRD_ENA << (2 * cs)); in ddr3_write_leveling_single_cs()
1179 reg = (reg_read(REG_TRAINING_WL_ADDR) & REG_TRAINING_WL_CS_MASK) | cs; in ddr3_write_leveling_single_cs()
1185 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, 0, 0); in ddr3_write_leveling_single_cs()
1225 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, phase, in ddr3_write_leveling_single_cs()
1267 if (dram_info->wl_val[cs][pup][S] == 0) { in ddr3_write_leveling_single_cs()
1269 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_single_cs()
1271 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_single_cs()
1279 && (dram_info->wl_val[cs][pup][S] == 0)) { in ddr3_write_leveling_single_cs()
1285 dram_info->wl_val[cs][pup][S] = 1; in ddr3_write_leveling_single_cs()
1301 DEBUG_WL_C("DDR3 - Write Leveling - Results for CS - ", (u32) cs, 1); in ddr3_write_leveling_single_cs()
1306 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][P], 1); in ddr3_write_leveling_single_cs()
1308 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][D], 2); in ddr3_write_leveling_single_cs()
1322 phase = dram_info->wl_val[cs][pup][P]; in ddr3_write_leveling_single_cs()
1323 delay = dram_info->wl_val[cs][pup][D]; in ddr3_write_leveling_single_cs()
1324 ddr3_write_pup_reg(PUP_WL_MODE, cs, pup_num, phase, delay); in ddr3_write_leveling_single_cs()