Lines Matching refs:cs
71 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
72 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
73 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
76 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
77 ddr_out32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
78 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
81 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
82 ddr_out32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
83 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
86 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
87 ddr_out32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
88 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
203 if (!(regs->cs[i].config & 0x80000000)) in fsl_ddr_set_memctl_regs()
206 ((regs->cs[i].config >> 14) & 0x3) + 2 + in fsl_ddr_set_memctl_regs()
207 ((regs->cs[i].config >> 8) & 0x7) + 12 + in fsl_ddr_set_memctl_regs()
208 ((regs->cs[i].config >> 0) & 0x7) + 8 + in fsl_ddr_set_memctl_regs()
212 if (regs->cs[0].config & 0x20000000) { in fsl_ddr_set_memctl_regs()