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/rk3399_rockchip-uboot/board/micronas/vct/vctv/
H A Dreg_ebi.h17 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
19 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
21 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
23 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
25 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
27 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
29 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
31 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
33 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
35 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
[all …]
/rk3399_rockchip-uboot/board/micronas/vct/vcth2/
H A Dreg_ebi.h17 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
19 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
21 #define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) argument
23 #define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) argument
25 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
27 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
29 #define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) argument
31 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
33 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
35 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
[all …]
/rk3399_rockchip-uboot/board/micronas/vct/vcth/
H A Dreg_ebi.h17 #define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) argument
19 #define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) argument
21 #define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) argument
23 #define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) argument
25 #define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) argument
27 #define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) argument
29 #define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) argument
31 #define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) argument
33 #define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) argument
35 #define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) argument
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H A Dreg_fwsram.h22 #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) argument
24 #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) argument
26 #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) argument
28 #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) argument
30 #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) argument
32 #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) argument
34 #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) argument
36 #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) argument
38 #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) argument
40 #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) argument
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H A Dreg_scc.h57 #define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) argument
59 #define SCC_RESET(base) ((base) + SCC_RESET_OFFS) argument
61 #define SCC_VCID(base) ((base) + SCC_VCID_OFFS) argument
63 #define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) argument
65 #define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) argument
67 #define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) argument
69 #define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) argument
71 #define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) argument
73 #define SCC_CMD(base) ((base) + SCC_CMD_OFFS) argument
75 #define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) argument
[all …]
/rk3399_rockchip-uboot/drivers/i2c/
H A Dsh_sh7734_i2c.c29 static struct sh_i2c *base; variable
68 static void sh_i2c_send_stop(struct sh_i2c *base) in sh_i2c_send_stop() argument
70 clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP); in sh_i2c_send_stop()
73 static int check_icsr_bits(struct sh_i2c *base, u8 bits) in check_icsr_bits() argument
78 if (bits & readb(&base->icsr)) in check_icsr_bits()
86 static int check_stop(struct sh_i2c *base) in check_stop() argument
88 int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP); in check_stop()
89 clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); in check_stop()
94 static int check_tend(struct sh_i2c *base, int stop) in check_tend() argument
96 int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND); in check_tend()
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H A Dmv_i2c.c69 static void i2c_reset(struct mv_i2c *base) in i2c_reset() argument
74 icr_mode = readl(&base->icr) & ICR_MODE_MASK; in i2c_reset()
75 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ in i2c_reset()
76 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */ in i2c_reset()
78 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ in i2c_reset()
82 writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ in i2c_reset()
84 writel(I2C_ICR_INIT | icr_mode, &base->icr); in i2c_reset()
85 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ in i2c_reset()
86 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */ in i2c_reset()
96 static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask, in i2c_isr_set_cleared() argument
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H A Dintel_i2c.c61 u32 base; member
65 static int smbus_wait_until_ready(u32 base) in smbus_wait_until_ready() argument
72 byte = inb(base + SMBHSTSTAT); in smbus_wait_until_ready()
80 static int smbus_wait_until_done(u32 base) in smbus_wait_until_done() argument
87 byte = inb(base + SMBHSTSTAT); in smbus_wait_until_done()
95 static int smbus_block_read(u32 base, u8 dev, u8 *buffer, in smbus_block_read() argument
104 if (smbus_wait_until_ready(base) < 0) in smbus_block_read()
110 inb(base + SMBHSTCTL); in smbus_block_read()
113 outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD); in smbus_block_read()
115 outb(offset & 0xff, base + SMBHSTCMD); in smbus_block_read()
[all …]
H A Dfsl_i2c.c119 static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, in set_i2c_bus_speed() argument
180 writeb(dfsr, &base->dfsrr); /* set default filter */ in set_i2c_bus_speed()
181 writeb(fdr, &base->fdr); /* set bus speed */ in set_i2c_bus_speed()
191 writeb(fdr, &base->fdr); /* set bus speed */ in set_i2c_bus_speed()
209 static int fsl_i2c_fixup(const struct fsl_i2c_base *base) in fsl_i2c_fixup() argument
223 writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr); in fsl_i2c_fixup()
226 while (!(readb(&base->sr) & I2C_SR_MBB)) { in fsl_i2c_fixup()
231 if (readb(&base->sr) & I2C_SR_MAL) { in fsl_i2c_fixup()
233 writeb(0, &base->cr); in fsl_i2c_fixup()
235 writeb(I2C_CR_MSTA | flags, &base->cr); in fsl_i2c_fixup()
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H A Dlpc32xx_i2c.c54 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base *base, in __i2c_set_bus_speed() argument
73 writel(half_period, &base->clk_hi); in __i2c_set_bus_speed()
74 writel(half_period, &base->clk_lo); in __i2c_set_bus_speed()
79 static void __i2c_init(struct lpc32xx_i2c_base *base, in __i2c_init() argument
83 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl); in __i2c_init()
85 __i2c_set_bus_speed(base, requested_speed, chip); in __i2c_init()
89 static int __i2c_probe_chip(struct lpc32xx_i2c_base *base, u8 dev) in __i2c_probe_chip() argument
94 writel(LPC32XX_I2C_SOFT_RESET, &base->ctrl); in __i2c_probe_chip()
95 while (readl(&base->ctrl) & LPC32XX_I2C_SOFT_RESET) in __i2c_probe_chip()
99 &base->tx); in __i2c_probe_chip()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/
H A Dpll-base-ld20.c34 void __iomem *base; in uniphier_ld20_sscpll_init() local
37 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_init()
38 if (!base) in uniphier_ld20_sscpll_init()
42 tmp = readl(base); /* SSCPLLCTRL */ in uniphier_ld20_sscpll_init()
46 writel(tmp, base); in uniphier_ld20_sscpll_init()
48 tmp = readl(base + 4); in uniphier_ld20_sscpll_init()
55 tmp = readl(base + 4); /* SSCPLLCTRL2 */ in uniphier_ld20_sscpll_init()
57 writel(tmp, base + 4); in uniphier_ld20_sscpll_init()
59 iounmap(base); in uniphier_ld20_sscpll_init()
66 void __iomem *base; in uniphier_ld20_sscpll_ssc_en() local
[all …]
/rk3399_rockchip-uboot/drivers/net/
H A Dtsi108_eth.c45 #define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset)))) argument
47 #define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000) argument
62 #define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004) argument
73 #define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010) argument
75 #define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020) argument
81 #define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024) argument
85 #define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028) argument
86 #define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c) argument
87 #define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030) argument
89 #define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034) argument
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H A Dne2000_base.c106 u8* base; in dp83902a_init() local
113 base = dp->base; in dp83902a_init()
114 if (!base) in dp83902a_init()
122 DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ in dp83902a_init()
125 DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); in dp83902a_init()
126 DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ in dp83902a_init()
146 u8 *base = dp->base; in dp83902a_stop() local
150 DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ in dp83902a_stop()
151 DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ in dp83902a_stop()
152 DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ in dp83902a_stop()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dddr3.c25 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) in ddr3_init_ddrphy() argument
29 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
33 __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); in ddr3_init_ddrphy()
35 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
38 __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
40 __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); in ddr3_init_ddrphy()
41 __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); in ddr3_init_ddrphy()
42 __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); in ddr3_init_ddrphy()
43 __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); in ddr3_init_ddrphy()
45 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
[all …]
/rk3399_rockchip-uboot/drivers/serial/
H A Dserial_mvebu_a3700.c13 void __iomem *base; member
37 void __iomem *base = plat->base; in mvebu_serial_putc() local
39 while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL) in mvebu_serial_putc()
42 writel(ch, base + UART_TX_REG); in mvebu_serial_putc()
50 void __iomem *base = plat->base; in mvebu_serial_getc() local
52 while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)) in mvebu_serial_getc()
55 return readl(base + UART_RX_REG) & 0xff; in mvebu_serial_getc()
61 void __iomem *base = plat->base; in mvebu_serial_pending() local
63 if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY) in mvebu_serial_pending()
72 void __iomem *base = plat->base; in mvebu_serial_setbrg() local
[all …]
H A Dserial_bcm6345.c86 void __iomem *base; member
91 static void bcm6345_serial_enable(void __iomem *base) in bcm6345_serial_enable() argument
93 setbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
98 static void bcm6345_serial_disable(void __iomem *base) in bcm6345_serial_disable() argument
100 clrbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
105 static void bcm6345_serial_flush(void __iomem *base) in bcm6345_serial_flush() argument
108 setbits_be32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
112 readl_be(base + UART_FIFO_REG); in bcm6345_serial_flush()
115 static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate) in bcm6345_serial_init() argument
120 bcm6345_serial_disable(base); in bcm6345_serial_init()
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H A Dserial_pic32.c41 void __iomem *base; member
49 static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate) in pic32_serial_init() argument
54 wait_for_bit_le32(base + U_STA, UART_TX_EMPTY, in pic32_serial_init()
58 writel(UART_TX_BRK, base + U_STASET); in pic32_serial_init()
61 writel(0, base + U_MOD); in pic32_serial_init()
62 writel(0, base + U_STA); in pic32_serial_init()
65 writel(div - 1, base + U_BRG); in pic32_serial_init()
68 writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET); in pic32_serial_init()
71 writel(UART_ENABLE, base + U_MODSET); in pic32_serial_init()
76 static int pic32_uart_pending_input(void __iomem *base) in pic32_uart_pending_input() argument
[all …]
H A Dserial_linflexuart.c42 static void _linflex_serial_setbrg(struct linflex_fsl *base, int baudrate) in _linflex_serial_setbrg() argument
53 __raw_writel(ibr, &base->linibrr); in _linflex_serial_setbrg()
54 __raw_writel(fbr, &base->linfbrr); in _linflex_serial_setbrg()
57 static int _linflex_serial_getc(struct linflex_fsl *base) in _linflex_serial_getc() argument
61 if (!(__raw_readb(&base->uartsr) & UARTSR_DRF)) in _linflex_serial_getc()
64 if (!(__raw_readl(&base->uartsr) & UARTSR_RMB)) in _linflex_serial_getc()
67 c = __raw_readl(&base->bdrm); in _linflex_serial_getc()
68 __raw_writeb((__raw_readb(&base->uartsr) | (UARTSR_DRF | UARTSR_RMB)), in _linflex_serial_getc()
69 &base->uartsr); in _linflex_serial_getc()
73 static int _linflex_serial_putc(struct linflex_fsl *base, const char c) in _linflex_serial_putc() argument
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/rk3399_rockchip-uboot/drivers/bios_emulator/
H A Dbiosemui.h67 #define readb_le(base) *((u8*)(base)) argument
68 #define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) argument
69 #define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ argument
70 ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24))
71 #define writeb_le(base, v) *((u8*)(base)) = (v) argument
72 #define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
73 writeb_le(base + 1, (v >> 8) & 0xff)
74 #define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ argument
75 writeb_le(base + 1, (v >> 8) & 0xff), \
76 writeb_le(base + 2, (v >> 16) & 0xff), \
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/rk3399_rockchip-uboot/lib/
H A Dlmb.c26 (long long unsigned)lmb->memory.region[i].base); in lmb_dump_all()
37 (long long unsigned)lmb->reserved.region[i].base); in lmb_dump_all()
64 phys_addr_t base1 = rgn->region[r1].base; in lmb_regions_adjacent()
66 phys_addr_t base2 = rgn->region[r2].base; in lmb_regions_adjacent()
77 rgn->region[i].base = rgn->region[i + 1].base; in lmb_remove_region()
96 lmb->memory.region[0].base = 0; in lmb_init()
102 lmb->reserved.region[0].base = 0; in lmb_init()
109 static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size) in lmb_add_region() argument
115 rgn->region[0].base = base; in lmb_add_region()
122 phys_addr_t rgnbase = rgn->region[i].base; in lmb_add_region()
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H A Dstrto.c17 static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) in _parse_integer_fixup_radix() argument
19 if (*base == 0) { in _parse_integer_fixup_radix()
22 *base = 16; in _parse_integer_fixup_radix()
24 *base = 8; in _parse_integer_fixup_radix()
26 *base = 10; in _parse_integer_fixup_radix()
28 if (*base == 16 && s[0] == '0' && tolower(s[1]) == 'x') in _parse_integer_fixup_radix()
34 unsigned int base) in simple_strtoul() argument
39 cp = _parse_integer_fixup_radix(cp, &base); in simple_strtoul()
42 ? toupper(*cp) : *cp)-'A'+10) < base) { in simple_strtoul()
43 result = result*base + value; in simple_strtoul()
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H A Dsysmem.c54 return ((sub->base >= main->base) && in sysmem_is_sub_region()
55 (sub->base + sub->size <= main->base + main->size)); in sysmem_is_sub_region()
81 (ulong)lmb->memory.region[i].base, in sysmem_dump()
82 (ulong)lmb->memory.region[i].base + in sysmem_dump()
99 (mem->base + mem->size - sizeof(*check)); in sysmem_dump()
103 (mem->base - sizeof(*check)); in sysmem_dump()
111 mem->orig_base != mem->base ? "<*>" : ""); in sysmem_dump()
127 mem->orig_base != mem->base ? "<*>" : ""); in sysmem_dump()
151 (ulong)lmb->reserved.region[i].base, in sysmem_dump()
152 (ulong)lmb->reserved.region[i].base + in sysmem_dump()
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/rk3399_rockchip-uboot/drivers/pch/
H A Dpch9.c27 u32 base; in pch9_get_gpio_base() local
39 dm_pci_read_config32(dev, GPIO_BASE, &base); in pch9_get_gpio_base()
40 if (base == 0x00000000 || base == 0xffffffff) { in pch9_get_gpio_base()
51 *gbasep = base & 1 ? base & ~3 : base & ~15; in pch9_get_gpio_base()
58 u32 base; in pch9_get_io_base() local
60 dm_pci_read_config32(dev, IO_BASE, &base); in pch9_get_io_base()
61 if (base == 0x00000000 || base == 0xffffffff) { in pch9_get_io_base()
66 *iobasep = base & 1 ? base & ~3 : base & ~15; in pch9_get_io_base()
/rk3399_rockchip-uboot/drivers/soc/keystone/
H A Dkeystone_serdes.c109 static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size) in ks2_serdes_cfg_setup() argument
114 ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask); in ks2_serdes_cfg_setup()
117 static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane, in ks2_serdes_lane_config() argument
123 ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane), in ks2_serdes_lane_config()
127 static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes) in ks2_serdes_init_cfg() argument
131 ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM); in ks2_serdes_init_cfg()
132 ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM); in ks2_serdes_init_cfg()
135 ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i); in ks2_serdes_init_cfg()
140 static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes) in ks2_serdes_cmu_comlane_enable() argument
143 ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET); in ks2_serdes_cmu_comlane_enable()
[all …]
/rk3399_rockchip-uboot/board/intel/galileo/
H A Dgalileo.c24 u32 base, port, val; in board_assert_perst() local
27 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); in board_assert_perst()
28 base = (base & 0xffff) & ~0x7f; in board_assert_perst()
31 port = base + 0x20; in board_assert_perst()
37 port = base + 0x24; in board_assert_perst()
43 port = base + 0x28; in board_assert_perst()
51 u32 base, port, val; in board_deassert_perst() local
54 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base); in board_deassert_perst()
55 base = (base & 0xffff) & ~0x7f; in board_deassert_perst()
58 port = base + 0x28; in board_deassert_perst()

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