25 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)  in ddr3_init_ddrphy()  argument
29 	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)  in ddr3_init_ddrphy()
33 	__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);  in ddr3_init_ddrphy()
35 	tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);  in ddr3_init_ddrphy()
38 	__raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);  in ddr3_init_ddrphy()
40 	__raw_writel(phy_cfg->ptr0,   base + KS2_DDRPHY_PTR0_OFFSET);  in ddr3_init_ddrphy()
41 	__raw_writel(phy_cfg->ptr1,   base + KS2_DDRPHY_PTR1_OFFSET);  in ddr3_init_ddrphy()
42 	__raw_writel(phy_cfg->ptr3,  base + KS2_DDRPHY_PTR3_OFFSET);  in ddr3_init_ddrphy()
43 	__raw_writel(phy_cfg->ptr4,  base + KS2_DDRPHY_PTR4_OFFSET);  in ddr3_init_ddrphy()
45 	tmp =  __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);  in ddr3_init_ddrphy()
48 	__raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);  in ddr3_init_ddrphy()
50 	__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);  in ddr3_init_ddrphy()
51 	__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);  in ddr3_init_ddrphy()
52 	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);  in ddr3_init_ddrphy()
53 	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);  in ddr3_init_ddrphy()
54 	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);  in ddr3_init_ddrphy()
55 	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);  in ddr3_init_ddrphy()
56 	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);  in ddr3_init_ddrphy()
57 	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);  in ddr3_init_ddrphy()
59 	__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);  in ddr3_init_ddrphy()
60 	__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);  in ddr3_init_ddrphy()
61 	__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);  in ddr3_init_ddrphy()
63 	__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);  in ddr3_init_ddrphy()
64 	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)  in ddr3_init_ddrphy()
68 		clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,  in ddr3_init_ddrphy()
72 		clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,  in ddr3_init_ddrphy()
76 		clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,  in ddr3_init_ddrphy()
80 		clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,  in ddr3_init_ddrphy()
84 		clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,  in ddr3_init_ddrphy()
88 		clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,  in ddr3_init_ddrphy()
92 		clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,  in ddr3_init_ddrphy()
97 	__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);  in ddr3_init_ddrphy()
98 	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)  in ddr3_init_ddrphy()
102 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)  in ddr3_init_ddremif()  argument
104 	__raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);  in ddr3_init_ddremif()
105 	__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);  in ddr3_init_ddremif()
106 	__raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);  in ddr3_init_ddremif()
107 	__raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);  in ddr3_init_ddremif()
108 	__raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);  in ddr3_init_ddremif()
109 	__raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);  in ddr3_init_ddremif()
110 	__raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);  in ddr3_init_ddremif()
113 int ddr3_ecc_support_rmw(u32 base)  in ddr3_ecc_support_rmw()  argument
115 	u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);  in ddr3_ecc_support_rmw()
125 static void ddr3_ecc_config(u32 base, u32 value)  in ddr3_ecc_config()  argument
129 	__raw_writel(value,  base + KS2_DDR3_ECC_CTRL_OFFSET);  in ddr3_ecc_config()
134 		data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);  in ddr3_ecc_config()
135 		__raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);  in ddr3_ecc_config()
140 			     base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);  in ddr3_ecc_config()
145 			     base + KS2_DDR3_ECC_INT_STATUS_OFFSET);  in ddr3_ecc_config()
149 static void ddr3_reset_data(u32 base, u32 ddr3_size)  in ddr3_reset_data()  argument
198 					     base >> KS2_MSMC_SEG_SIZE_SHIFT,  in ddr3_reset_data()
203 					     base >> KS2_MSMC_SEG_SIZE_SHIFT,  in ddr3_reset_data()
217 		for (dst = base, blks = 0; blks < edma_blks;  in ddr3_reset_data()
239 static void ddr3_ecc_init_range(u32 base)  in ddr3_ecc_init_range()  argument
242 	u32 rmw = ddr3_ecc_support_rmw(base);  in ddr3_ecc_init_range()
247 	__raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);  in ddr3_ecc_init_range()
249 	ddr3_ecc_config(base, ecc_val);  in ddr3_ecc_init_range()
252 void ddr3_enable_ecc(u32 base, int test)  in ddr3_enable_ecc()  argument
255 	u32 rmw = ddr3_ecc_support_rmw(base);  in ddr3_enable_ecc()
269 	ddr3_ecc_config(base, ecc_val);  in ddr3_enable_ecc()
272 void ddr3_disable_ecc(u32 base)  in ddr3_disable_ecc()  argument
274 	ddr3_ecc_config(base, 0);  in ddr3_disable_ecc()
278 static void cic_init(u32 base)  in cic_init()  argument
281 	__raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);  in cic_init()
284 	__raw_writel(0, base + KS2_CIC_CTRL);  in cic_init()
285 	__raw_writel(0, base + KS2_CIC_HOST_CTRL);  in cic_init()
288 	__raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);  in cic_init()
291 static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)  in cic_map_cic_to_gic()  argument
294 	__raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);  in cic_map_cic_to_gic()
297 	__raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);  in cic_map_cic_to_gic()
300 	__raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);  in cic_map_cic_to_gic()
303 static void ddr3_map_ecc_cic2_irq(u32 base)  in ddr3_map_ecc_cic2_irq()  argument
305 	cic_init(base);  in ddr3_map_ecc_cic2_irq()
306 	cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,  in ddr3_map_ecc_cic2_irq()
311 void ddr3_init_ecc(u32 base, u32 ddr3_size)  in ddr3_init_ecc()  argument
313 	if (!ddr3_ecc_support_rmw(base)) {  in ddr3_init_ecc()
314 		ddr3_disable_ecc(base);  in ddr3_init_ecc()
318 	ddr3_ecc_init_range(base);  in ddr3_init_ecc()
325 	ddr3_enable_ecc(base, 0);  in ddr3_init_ecc()
328 void ddr3_check_ecc_int(u32 base)  in ddr3_check_ecc_int()  argument
332 	u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);  in ddr3_check_ecc_int()
350 	value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);  in ddr3_check_ecc_int()
353 		value = __raw_readl(base +  in ddr3_check_ecc_int()