181afac12SSimon Glass /*
281afac12SSimon Glass * Copyright (C) 2014 Google, Inc
381afac12SSimon Glass *
481afac12SSimon Glass * SPDX-License-Identifier: GPL-2.0+
581afac12SSimon Glass */
681afac12SSimon Glass
781afac12SSimon Glass #include <common.h>
881afac12SSimon Glass #include <dm.h>
981afac12SSimon Glass #include <pch.h>
1081afac12SSimon Glass
11ec2af6f8SBin Meng #define GPIO_BASE 0x48
12*4f106bc8SBin Meng #define IO_BASE 0x4c
1381afac12SSimon Glass #define SBASE_ADDR 0x54
1481afac12SSimon Glass
pch9_get_spi_base(struct udevice * dev,ulong * sbasep)153e389d8bSBin Meng static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
1681afac12SSimon Glass {
1781afac12SSimon Glass uint32_t sbase_addr;
1881afac12SSimon Glass
1981afac12SSimon Glass dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
2081afac12SSimon Glass *sbasep = sbase_addr & 0xfffffe00;
2181afac12SSimon Glass
2281afac12SSimon Glass return 0;
2381afac12SSimon Glass }
2481afac12SSimon Glass
pch9_get_gpio_base(struct udevice * dev,u32 * gbasep)25ec2af6f8SBin Meng static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
26ec2af6f8SBin Meng {
27ec2af6f8SBin Meng u32 base;
28ec2af6f8SBin Meng
29ec2af6f8SBin Meng /*
30ec2af6f8SBin Meng * GPIO_BASE moved to its current offset with ICH6, but prior to
31ec2af6f8SBin Meng * that it was unused (or undocumented). Check that it looks
32ec2af6f8SBin Meng * okay: not all ones or zeros.
33ec2af6f8SBin Meng *
34ec2af6f8SBin Meng * Note we don't need check bit0 here, because the Tunnel Creek
35ec2af6f8SBin Meng * GPIO base address register bit0 is reserved (read returns 0),
36ec2af6f8SBin Meng * while on the Ivybridge the bit0 is used to indicate it is an
37ec2af6f8SBin Meng * I/O space.
38ec2af6f8SBin Meng */
39ec2af6f8SBin Meng dm_pci_read_config32(dev, GPIO_BASE, &base);
40ec2af6f8SBin Meng if (base == 0x00000000 || base == 0xffffffff) {
41ec2af6f8SBin Meng debug("%s: unexpected BASE value\n", __func__);
42ec2af6f8SBin Meng return -ENODEV;
43ec2af6f8SBin Meng }
44ec2af6f8SBin Meng
45ec2af6f8SBin Meng /*
46ec2af6f8SBin Meng * Okay, I guess we're looking at the right device. The actual
47ec2af6f8SBin Meng * GPIO registers are in the PCI device's I/O space, starting
48ec2af6f8SBin Meng * at the offset that we just read. Bit 0 indicates that it's
49ec2af6f8SBin Meng * an I/O address, not a memory address, so mask that off.
50ec2af6f8SBin Meng */
51ec2af6f8SBin Meng *gbasep = base & 1 ? base & ~3 : base & ~15;
52ec2af6f8SBin Meng
53ec2af6f8SBin Meng return 0;
54ec2af6f8SBin Meng }
55ec2af6f8SBin Meng
pch9_get_io_base(struct udevice * dev,u32 * iobasep)56*4f106bc8SBin Meng static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
57*4f106bc8SBin Meng {
58*4f106bc8SBin Meng u32 base;
59*4f106bc8SBin Meng
60*4f106bc8SBin Meng dm_pci_read_config32(dev, IO_BASE, &base);
61*4f106bc8SBin Meng if (base == 0x00000000 || base == 0xffffffff) {
62*4f106bc8SBin Meng debug("%s: unexpected BASE value\n", __func__);
63*4f106bc8SBin Meng return -ENODEV;
64*4f106bc8SBin Meng }
65*4f106bc8SBin Meng
66*4f106bc8SBin Meng *iobasep = base & 1 ? base & ~3 : base & ~15;
67*4f106bc8SBin Meng
68*4f106bc8SBin Meng return 0;
69*4f106bc8SBin Meng }
70*4f106bc8SBin Meng
7181afac12SSimon Glass static const struct pch_ops pch9_ops = {
723e389d8bSBin Meng .get_spi_base = pch9_get_spi_base,
73ec2af6f8SBin Meng .get_gpio_base = pch9_get_gpio_base,
74*4f106bc8SBin Meng .get_io_base = pch9_get_io_base,
7581afac12SSimon Glass };
7681afac12SSimon Glass
7781afac12SSimon Glass static const struct udevice_id pch9_ids[] = {
7881afac12SSimon Glass { .compatible = "intel,pch9" },
7981afac12SSimon Glass { }
8081afac12SSimon Glass };
8181afac12SSimon Glass
8281afac12SSimon Glass U_BOOT_DRIVER(pch9_drv) = {
8381afac12SSimon Glass .name = "intel-pch9",
8481afac12SSimon Glass .id = UCLASS_PCH,
8581afac12SSimon Glass .of_match = pch9_ids,
8681afac12SSimon Glass .ops = &pch9_ops,
8781afac12SSimon Glass };
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