xref: /rk3399_rockchip-uboot/drivers/serial/serial_pic32.c (revision b491b49882fc71838b46c47a860daf2978c80be4)
19e160ee8SPaul Thacker /*
29e160ee8SPaul Thacker  * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
39e160ee8SPaul Thacker  *
49e160ee8SPaul Thacker  * SPDX-License-Identifier:	GPL-2.0+
59e160ee8SPaul Thacker  *
69e160ee8SPaul Thacker  */
79e160ee8SPaul Thacker #include <common.h>
89e160ee8SPaul Thacker #include <clk.h>
99e160ee8SPaul Thacker #include <dm.h>
109e160ee8SPaul Thacker #include <serial.h>
119e160ee8SPaul Thacker #include <wait_bit.h>
129e160ee8SPaul Thacker #include <mach/pic32.h>
139e160ee8SPaul Thacker #include <dt-bindings/clock/microchip,clock.h>
149e160ee8SPaul Thacker 
159e160ee8SPaul Thacker DECLARE_GLOBAL_DATA_PTR;
169e160ee8SPaul Thacker 
179e160ee8SPaul Thacker /* UART Control Registers */
189e160ee8SPaul Thacker #define U_MOD		0x00
199e160ee8SPaul Thacker #define U_MODCLR	(U_MOD + _CLR_OFFSET)
209e160ee8SPaul Thacker #define U_MODSET	(U_MOD + _SET_OFFSET)
219e160ee8SPaul Thacker #define U_STA		0x10
229e160ee8SPaul Thacker #define U_STACLR	(U_STA + _CLR_OFFSET)
239e160ee8SPaul Thacker #define U_STASET	(U_STA + _SET_OFFSET)
249e160ee8SPaul Thacker #define U_TXR		0x20
259e160ee8SPaul Thacker #define U_RXR		0x30
269e160ee8SPaul Thacker #define U_BRG		0x40
279e160ee8SPaul Thacker 
289e160ee8SPaul Thacker /* U_MOD bits */
299e160ee8SPaul Thacker #define UART_ENABLE		BIT(15)
309e160ee8SPaul Thacker 
319e160ee8SPaul Thacker /* U_STA bits */
329e160ee8SPaul Thacker #define UART_RX_ENABLE		BIT(12)
339e160ee8SPaul Thacker #define UART_TX_BRK		BIT(11)
349e160ee8SPaul Thacker #define UART_TX_ENABLE		BIT(10)
359e160ee8SPaul Thacker #define UART_TX_FULL		BIT(9)
369e160ee8SPaul Thacker #define UART_TX_EMPTY		BIT(8)
379e160ee8SPaul Thacker #define UART_RX_OVER		BIT(1)
389e160ee8SPaul Thacker #define UART_RX_DATA_AVAIL	BIT(0)
399e160ee8SPaul Thacker 
409e160ee8SPaul Thacker struct pic32_uart_priv {
419e160ee8SPaul Thacker 	void __iomem *base;
429e160ee8SPaul Thacker 	ulong uartclk;
439e160ee8SPaul Thacker };
449e160ee8SPaul Thacker 
459e160ee8SPaul Thacker /*
469e160ee8SPaul Thacker  * Initialize the serial port with the given baudrate.
479e160ee8SPaul Thacker  * The settings are always 8 data bits, no parity, 1 stop bit, no start bits.
489e160ee8SPaul Thacker  */
pic32_serial_init(void __iomem * base,ulong clk,u32 baudrate)499e160ee8SPaul Thacker static int pic32_serial_init(void __iomem *base, ulong clk, u32 baudrate)
509e160ee8SPaul Thacker {
519e160ee8SPaul Thacker 	u32 div = DIV_ROUND_CLOSEST(clk, baudrate * 16);
529e160ee8SPaul Thacker 
539e160ee8SPaul Thacker 	/* wait for TX FIFO to empty */
54*b491b498SJon Lin 	wait_for_bit_le32(base + U_STA, UART_TX_EMPTY,
559e160ee8SPaul Thacker 			  true, CONFIG_SYS_HZ, false);
569e160ee8SPaul Thacker 
579e160ee8SPaul Thacker 	/* send break */
589e160ee8SPaul Thacker 	writel(UART_TX_BRK, base + U_STASET);
599e160ee8SPaul Thacker 
609e160ee8SPaul Thacker 	/* disable and clear mode */
619e160ee8SPaul Thacker 	writel(0, base + U_MOD);
629e160ee8SPaul Thacker 	writel(0, base + U_STA);
639e160ee8SPaul Thacker 
649e160ee8SPaul Thacker 	/* set baud rate generator */
659e160ee8SPaul Thacker 	writel(div - 1, base + U_BRG);
669e160ee8SPaul Thacker 
679e160ee8SPaul Thacker 	/* enable the UART for TX and RX */
689e160ee8SPaul Thacker 	writel(UART_TX_ENABLE | UART_RX_ENABLE, base + U_STASET);
699e160ee8SPaul Thacker 
709e160ee8SPaul Thacker 	/* enable the UART */
719e160ee8SPaul Thacker 	writel(UART_ENABLE, base + U_MODSET);
729e160ee8SPaul Thacker 	return 0;
739e160ee8SPaul Thacker }
749e160ee8SPaul Thacker 
759e160ee8SPaul Thacker /* Check whether any char pending in RX fifo */
pic32_uart_pending_input(void __iomem * base)769e160ee8SPaul Thacker static int pic32_uart_pending_input(void __iomem *base)
779e160ee8SPaul Thacker {
789e160ee8SPaul Thacker 	/* check if rx buffer overrun error has occurred */
799e160ee8SPaul Thacker 	if (readl(base + U_STA) & UART_RX_OVER) {
809e160ee8SPaul Thacker 		readl(base + U_RXR);
819e160ee8SPaul Thacker 
829e160ee8SPaul Thacker 		/* clear overrun error to keep receiving */
839e160ee8SPaul Thacker 		writel(UART_RX_OVER, base + U_STACLR);
849e160ee8SPaul Thacker 	}
859e160ee8SPaul Thacker 
869e160ee8SPaul Thacker 	/* In PIC32 there is no way to know number of outstanding
879e160ee8SPaul Thacker 	 * chars in rx-fifo. Only it can be known whether there is any.
889e160ee8SPaul Thacker 	 */
899e160ee8SPaul Thacker 	return readl(base + U_STA) & UART_RX_DATA_AVAIL;
909e160ee8SPaul Thacker }
919e160ee8SPaul Thacker 
pic32_uart_pending(struct udevice * dev,bool input)929e160ee8SPaul Thacker static int pic32_uart_pending(struct udevice *dev, bool input)
939e160ee8SPaul Thacker {
949e160ee8SPaul Thacker 	struct pic32_uart_priv *priv = dev_get_priv(dev);
959e160ee8SPaul Thacker 
969e160ee8SPaul Thacker 	if (input)
979e160ee8SPaul Thacker 		return pic32_uart_pending_input(priv->base);
989e160ee8SPaul Thacker 
999e160ee8SPaul Thacker 	return !(readl(priv->base + U_STA) & UART_TX_EMPTY);
1009e160ee8SPaul Thacker }
1019e160ee8SPaul Thacker 
pic32_uart_setbrg(struct udevice * dev,int baudrate)1029e160ee8SPaul Thacker static int pic32_uart_setbrg(struct udevice *dev, int baudrate)
1039e160ee8SPaul Thacker {
1049e160ee8SPaul Thacker 	struct pic32_uart_priv *priv = dev_get_priv(dev);
1059e160ee8SPaul Thacker 
1069e160ee8SPaul Thacker 	return pic32_serial_init(priv->base, priv->uartclk, baudrate);
1079e160ee8SPaul Thacker }
1089e160ee8SPaul Thacker 
pic32_uart_putc(struct udevice * dev,const char ch)1099e160ee8SPaul Thacker static int pic32_uart_putc(struct udevice *dev, const char ch)
1109e160ee8SPaul Thacker {
1119e160ee8SPaul Thacker 	struct pic32_uart_priv *priv = dev_get_priv(dev);
1129e160ee8SPaul Thacker 
1139e160ee8SPaul Thacker 	/* Check if Tx FIFO is full */
1149e160ee8SPaul Thacker 	if (readl(priv->base + U_STA) & UART_TX_FULL)
1159e160ee8SPaul Thacker 		return -EAGAIN;
1169e160ee8SPaul Thacker 
1179e160ee8SPaul Thacker 	/* pump the char to tx buffer */
1189e160ee8SPaul Thacker 	writel(ch, priv->base + U_TXR);
1199e160ee8SPaul Thacker 
1209e160ee8SPaul Thacker 	return 0;
1219e160ee8SPaul Thacker }
1229e160ee8SPaul Thacker 
pic32_uart_getc(struct udevice * dev)1239e160ee8SPaul Thacker static int pic32_uart_getc(struct udevice *dev)
1249e160ee8SPaul Thacker {
1259e160ee8SPaul Thacker 	struct pic32_uart_priv *priv = dev_get_priv(dev);
1269e160ee8SPaul Thacker 
1279e160ee8SPaul Thacker 	/* return error if RX fifo is empty */
1289e160ee8SPaul Thacker 	if (!pic32_uart_pending_input(priv->base))
1299e160ee8SPaul Thacker 		return -EAGAIN;
1309e160ee8SPaul Thacker 
1319e160ee8SPaul Thacker 	/* read the character from rx buffer */
1329e160ee8SPaul Thacker 	return readl(priv->base + U_RXR) & 0xff;
1339e160ee8SPaul Thacker }
1349e160ee8SPaul Thacker 
pic32_uart_probe(struct udevice * dev)1359e160ee8SPaul Thacker static int pic32_uart_probe(struct udevice *dev)
1369e160ee8SPaul Thacker {
1379e160ee8SPaul Thacker 	struct pic32_uart_priv *priv = dev_get_priv(dev);
138135aa950SStephen Warren 	struct clk clk;
1399e160ee8SPaul Thacker 	fdt_addr_t addr;
1409e160ee8SPaul Thacker 	fdt_size_t size;
1419e160ee8SPaul Thacker 	int ret;
1429e160ee8SPaul Thacker 
1439e160ee8SPaul Thacker 	/* get address */
144e160f7d4SSimon Glass 	addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
145e160f7d4SSimon Glass 				    &size);
1469e160ee8SPaul Thacker 	if (addr == FDT_ADDR_T_NONE)
1479e160ee8SPaul Thacker 		return -EINVAL;
1489e160ee8SPaul Thacker 
1499e160ee8SPaul Thacker 	priv->base = ioremap(addr, size);
1509e160ee8SPaul Thacker 
1519e160ee8SPaul Thacker 	/* get clock rate */
152135aa950SStephen Warren 	ret = clk_get_by_index(dev, 0, &clk);
1539e160ee8SPaul Thacker 	if (ret < 0)
1549e160ee8SPaul Thacker 		return ret;
155135aa950SStephen Warren 	priv->uartclk = clk_get_rate(&clk);
156135aa950SStephen Warren 	clk_free(&clk);
1579e160ee8SPaul Thacker 
1589e160ee8SPaul Thacker 	/* initialize serial */
1599e160ee8SPaul Thacker 	return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
1609e160ee8SPaul Thacker }
1619e160ee8SPaul Thacker 
1629e160ee8SPaul Thacker static const struct dm_serial_ops pic32_uart_ops = {
1639e160ee8SPaul Thacker 	.putc		= pic32_uart_putc,
1649e160ee8SPaul Thacker 	.pending	= pic32_uart_pending,
1659e160ee8SPaul Thacker 	.getc		= pic32_uart_getc,
1669e160ee8SPaul Thacker 	.setbrg		= pic32_uart_setbrg,
1679e160ee8SPaul Thacker };
1689e160ee8SPaul Thacker 
1699e160ee8SPaul Thacker static const struct udevice_id pic32_uart_ids[] = {
1709e160ee8SPaul Thacker 	{ .compatible = "microchip,pic32mzda-uart" },
1719e160ee8SPaul Thacker 	{}
1729e160ee8SPaul Thacker };
1739e160ee8SPaul Thacker 
1749e160ee8SPaul Thacker U_BOOT_DRIVER(pic32_serial) = {
1759e160ee8SPaul Thacker 	.name		= "pic32-uart",
1769e160ee8SPaul Thacker 	.id		= UCLASS_SERIAL,
1779e160ee8SPaul Thacker 	.of_match	= pic32_uart_ids,
1789e160ee8SPaul Thacker 	.probe		= pic32_uart_probe,
1799e160ee8SPaul Thacker 	.ops		= &pic32_uart_ops,
1809e160ee8SPaul Thacker 	.flags		= DM_FLAG_PRE_RELOC,
1819e160ee8SPaul Thacker 	.priv_auto_alloc_size = sizeof(struct pic32_uart_priv),
1829e160ee8SPaul Thacker };
1839e160ee8SPaul Thacker 
1849e160ee8SPaul Thacker #ifdef CONFIG_DEBUG_UART_PIC32
1859e160ee8SPaul Thacker #include <debug_uart.h>
1869e160ee8SPaul Thacker 
_debug_uart_init(void)1879e160ee8SPaul Thacker static inline void _debug_uart_init(void)
1889e160ee8SPaul Thacker {
1899e160ee8SPaul Thacker 	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
1909e160ee8SPaul Thacker 
1919e160ee8SPaul Thacker 	pic32_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
1929e160ee8SPaul Thacker }
1939e160ee8SPaul Thacker 
_debug_uart_putc(int ch)1949e160ee8SPaul Thacker static inline void _debug_uart_putc(int ch)
1959e160ee8SPaul Thacker {
1969e160ee8SPaul Thacker 	writel(ch, CONFIG_DEBUG_UART_BASE + U_TXR);
1979e160ee8SPaul Thacker }
1989e160ee8SPaul Thacker 
1999e160ee8SPaul Thacker DEBUG_UART_FUNCS
2009e160ee8SPaul Thacker #endif
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