61 	u32 base;  member
65 static int smbus_wait_until_ready(u32 base)  in smbus_wait_until_ready()  argument
72 		byte = inb(base + SMBHSTSTAT);  in smbus_wait_until_ready()
80 static int smbus_wait_until_done(u32 base)  in smbus_wait_until_done()  argument
87 		byte = inb(base + SMBHSTSTAT);  in smbus_wait_until_done()
95 static int smbus_block_read(u32 base, u8 dev, u8 *buffer,  in smbus_block_read()  argument
104 	if (smbus_wait_until_ready(base) < 0)  in smbus_block_read()
110 	inb(base + SMBHSTCTL);  in smbus_block_read()
113 	outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD);  in smbus_block_read()
115 	outb(offset & 0xff, base + SMBHSTCMD);  in smbus_block_read()
117 	outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),  in smbus_block_read()
118 	     (base + SMBHSTCTL));  in smbus_block_read()
120 	outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);  in smbus_block_read()
123 	outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);  in smbus_block_read()
126 	if (smbus_wait_until_done(base) < 0) {  in smbus_block_read()
131 	count = inb(base + SMBHSTDAT0);  in smbus_block_read()
150 		buf_temp[i] = inb(base + SMBBLKDAT);  in smbus_block_read()
155 	if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))  in smbus_block_read()
161 static int smbus_block_write(u32 base, u8 dev, u8 *buffer,  in smbus_block_write()  argument
168 	if (smbus_wait_until_ready(base) < 0)  in smbus_block_write()
173 	outb(((dev & 0x7f) << 1) & ~0x01, base + SMBXMITADD);  in smbus_block_write()
175 	outb(offset, base + SMBHSTCMD);  in smbus_block_write()
177 	outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),  in smbus_block_write()
178 	     (base + SMBHSTCTL));  in smbus_block_write()
180 	outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);  in smbus_block_write()
183 	outb(len, base + SMBHSTDAT0);  in smbus_block_write()
187 		outb(*buffer++, base + SMBBLKDAT);  in smbus_block_write()
190 	outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);  in smbus_block_write()
193 	if (smbus_wait_until_done(base) < 0) {  in smbus_block_write()
199 	if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))  in smbus_block_write()
227 		return smbus_block_read(i2c->base, dmsg->addr, &dmsg->buf[0],  in intel_i2c_xfer()
230 		return smbus_block_write(i2c->base, dmsg->addr, &dmsg->buf[1],  in intel_i2c_xfer()
240 	return smbus_block_read(i2c->base, chip_addr, buf, 0, 1);  in intel_i2c_probe_chip()
251 	ulong base;  in intel_i2c_probe()  local
254 	priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,  in intel_i2c_probe()
256 	base = priv->base;  in intel_i2c_probe()
262 	outb(inb(base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, base + SMBHSTCTL);  in intel_i2c_probe()
265 	outb(inb(base + SMBAUXCTL) | SMBAUXCTL_E32B, base + SMBAUXCTL);  in intel_i2c_probe()