12a61eff6SStefan Roese /* 22a61eff6SStefan Roese * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering 32a61eff6SStefan Roese * 42a61eff6SStefan Roese * Copyright (C) 2006 Micronas GmbH 52a61eff6SStefan Roese * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 72a61eff6SStefan Roese */ 82a61eff6SStefan Roese 92a61eff6SStefan Roese #ifndef _REG_SCC_PREMIUM_H_ 102a61eff6SStefan Roese #define _REG_SCC_PREMIUM_H_ 112a61eff6SStefan Roese 122a61eff6SStefan Roese #define SCC0_BASE 0x00110000 132a61eff6SStefan Roese #define SCC1_BASE 0x00110080 142a61eff6SStefan Roese #define SCC2_BASE 0x00110100 152a61eff6SStefan Roese #define SCC3_BASE 0x00110180 162a61eff6SStefan Roese #define SCC4_BASE 0x00110200 172a61eff6SStefan Roese #define SCC5_BASE 0x00110280 182a61eff6SStefan Roese #define SCC6_BASE 0x00110300 192a61eff6SStefan Roese #define SCC7_BASE 0x00110380 202a61eff6SStefan Roese #define SCC8_BASE 0x00110400 212a61eff6SStefan Roese #define SCC9_BASE 0x00110480 222a61eff6SStefan Roese #define SCC10_BASE 0x00110500 232a61eff6SStefan Roese #define SCC11_BASE 0x00110580 242a61eff6SStefan Roese #define SCC12_BASE 0x00110600 252a61eff6SStefan Roese #define SCC13_BASE 0x00110680 262a61eff6SStefan Roese #define SCC14_BASE 0x00110700 272a61eff6SStefan Roese #define SCC15_BASE 0x00110780 282a61eff6SStefan Roese #define SCC16_BASE 0x00110800 292a61eff6SStefan Roese #define SCC17_BASE 0x00110880 302a61eff6SStefan Roese #define SCC18_BASE 0x00110900 312a61eff6SStefan Roese #define SCC19_BASE 0x00110980 322a61eff6SStefan Roese #define SCC20_BASE 0x00110a00 332a61eff6SStefan Roese #define SCC21_BASE 0x00110a80 342a61eff6SStefan Roese #define SCC22_BASE 0x00110b00 352a61eff6SStefan Roese #define SCC23_BASE 0x00110b80 362a61eff6SStefan Roese #define SCC24_BASE 0x00110c00 372a61eff6SStefan Roese #define SCC25_BASE 0x00110c80 382a61eff6SStefan Roese #define SCC26_BASE 0x00110d00 392a61eff6SStefan Roese #define SCC27_BASE 0x00110d80 402a61eff6SStefan Roese #define SCC28_BASE 0x00110e00 412a61eff6SStefan Roese #define SCC29_BASE 0x00110e80 422a61eff6SStefan Roese #define SCC30_BASE 0x00110f00 432a61eff6SStefan Roese #define SCC31_BASE 0x00110f80 442a61eff6SStefan Roese #define SCC32_BASE 0x00111000 452a61eff6SStefan Roese #define SCC33_BASE 0x00111080 462a61eff6SStefan Roese #define SCC34_BASE 0x00111100 472a61eff6SStefan Roese #define SCC35_BASE 0x00111180 482a61eff6SStefan Roese #define SCC36_BASE 0x00111200 492a61eff6SStefan Roese #define SCC37_BASE 0x00111280 502a61eff6SStefan Roese #define SCC38_BASE 0x00111300 512a61eff6SStefan Roese #define SCC39_BASE 0x00111380 522a61eff6SStefan Roese #define SCC40_BASE 0x00111400 532a61eff6SStefan Roese 542a61eff6SStefan Roese /* Relative offsets of the register adresses */ 552a61eff6SStefan Roese 562a61eff6SStefan Roese #define SCC_ENABLE_OFFS 0x00000000 572a61eff6SStefan Roese #define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) 582a61eff6SStefan Roese #define SCC_RESET_OFFS 0x00000004 592a61eff6SStefan Roese #define SCC_RESET(base) ((base) + SCC_RESET_OFFS) 602a61eff6SStefan Roese #define SCC_VCID_OFFS 0x00000008 612a61eff6SStefan Roese #define SCC_VCID(base) ((base) + SCC_VCID_OFFS) 622a61eff6SStefan Roese #define SCC_MCI_CFG_OFFS 0x0000000C 632a61eff6SStefan Roese #define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) 642a61eff6SStefan Roese #define SCC_PACKET_CFG1_OFFS 0x00000010 652a61eff6SStefan Roese #define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) 662a61eff6SStefan Roese #define SCC_PACKET_CFG2_OFFS 0x00000014 672a61eff6SStefan Roese #define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) 682a61eff6SStefan Roese #define SCC_PACKET_CFG3_OFFS 0x00000018 692a61eff6SStefan Roese #define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) 702a61eff6SStefan Roese #define SCC_DMA_CFG_OFFS 0x0000001C 712a61eff6SStefan Roese #define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) 722a61eff6SStefan Roese #define SCC_CMD_OFFS 0x00000020 732a61eff6SStefan Roese #define SCC_CMD(base) ((base) + SCC_CMD_OFFS) 742a61eff6SStefan Roese #define SCC_PRIO_OFFS 0x00000024 752a61eff6SStefan Roese #define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) 762a61eff6SStefan Roese #define SCC_DEBUG_OFFS 0x00000028 772a61eff6SStefan Roese #define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS) 782a61eff6SStefan Roese #define SCC_STATUS_OFFS 0x0000002C 792a61eff6SStefan Roese #define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS) 802a61eff6SStefan Roese #define SCC_IMR_OFFS 0x00000030 812a61eff6SStefan Roese #define SCC_IMR(base) ((base) + SCC_IMR_OFFS) 822a61eff6SStefan Roese #define SCC_ISR_OFFS 0x00000034 832a61eff6SStefan Roese #define SCC_ISR(base) ((base) + SCC_ISR_OFFS) 842a61eff6SStefan Roese #define SCC_DMA_OFFSET_OFFS 0x00000038 852a61eff6SStefan Roese #define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS) 862a61eff6SStefan Roese #define SCC_RS_CTLSTS_OFFS 0x0000003C 872a61eff6SStefan Roese #define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS) 882a61eff6SStefan Roese 892a61eff6SStefan Roese #endif 90