12a61eff6SStefan Roese /* 22a61eff6SStefan Roese * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering 32a61eff6SStefan Roese * 42a61eff6SStefan Roese * Copyright (C) 2006 Micronas GmbH 52a61eff6SStefan Roese * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 72a61eff6SStefan Roese */ 82a61eff6SStefan Roese 92a61eff6SStefan Roese /* 102a61eff6SStefan Roese * Premium & Platinum register addresses/definitions seem to be 112a61eff6SStefan Roese * identical, so we only need to use one file for both platforms. 122a61eff6SStefan Roese */ 132a61eff6SStefan Roese 142a61eff6SStefan Roese #ifndef _REG_FWSRAM_H_ 152a61eff6SStefan Roese #define _REG_FWSRAM_H_ 162a61eff6SStefan Roese 172a61eff6SStefan Roese #define FWSRAM_BASE 0x00030000 182a61eff6SStefan Roese 192a61eff6SStefan Roese /* Relative offsets of the register adresses */ 202a61eff6SStefan Roese 212a61eff6SStefan Roese #define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000 222a61eff6SStefan Roese #define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) 232a61eff6SStefan Roese #define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004 242a61eff6SStefan Roese #define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) 252a61eff6SStefan Roese #define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008 262a61eff6SStefan Roese #define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) 272a61eff6SStefan Roese #define FWSRAM_TOP_CID1_H_OFFS 0x0000200C 282a61eff6SStefan Roese #define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) 292a61eff6SStefan Roese #define FWSRAM_TOP_CID1_L_OFFS 0x00002010 302a61eff6SStefan Roese #define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) 312a61eff6SStefan Roese #define FWSRAM_TOP_CID2_H_OFFS 0x00002014 322a61eff6SStefan Roese #define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) 332a61eff6SStefan Roese #define FWSRAM_TOP_CID2_L_OFFS 0x00002018 342a61eff6SStefan Roese #define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) 352a61eff6SStefan Roese #define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C 362a61eff6SStefan Roese #define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) 372a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040 382a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) 392a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044 402a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) 412a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048 422a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS) 432a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C 442a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS) 452a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050 462a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS) 472a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054 482a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS) 492a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058 502a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS) 512a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C 522a61eff6SStefan Roese #define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS) 532a61eff6SStefan Roese #define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060 542a61eff6SStefan Roese #define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS) 552a61eff6SStefan Roese #define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064 562a61eff6SStefan Roese #define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS) 572a61eff6SStefan Roese #define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068 582a61eff6SStefan Roese #define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS) 592a61eff6SStefan Roese 602a61eff6SStefan Roese #endif 61