| /rk3399_rockchip-uboot/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 12 #define PLL_APLL 1 macro
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| H A D | rk3188-cru-common.h | 12 #define PLL_APLL 1 macro
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| H A D | rk3128-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3228-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3308-cru.h | 20 #define PLL_APLL 1 macro
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| H A D | rv1108-cru.h | 11 #define PLL_APLL 0 macro
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| H A D | px30-cru.h | 20 #define PLL_APLL 1 macro
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| H A D | rk3328-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rk3288-cru.h | 9 #define PLL_APLL 1 macro
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| H A D | rk1808-cru.h | 7 #define PLL_APLL 1 macro
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| H A D | rv1106-cru.h | 11 #define PLL_APLL 1 macro
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| H A D | rv1126-cru.h | 65 #define PLL_APLL 1 macro
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| H A D | rk3562-cru.h | 13 #define PLL_APLL 1 macro
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| H A D | rk3528-cru.h | 13 #define PLL_APLL 1 macro
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3128.c | 66 RK3128_CLK_DUMP(PLL_APLL, "apll", true),
81 [APLL] = PLL(pll_rk3036, PLL_APLL, RK2928_PLL_CON(0),
535 case PLL_APLL: in rk3128_clk_get_rate()
599 case PLL_APLL: in rk3128_clk_set_rate()
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| H A D | clk_rk322x.c | 67 RK322x_CLK_DUMP(PLL_APLL, "apll", true),
82 [APLL] = PLL(pll_rk3036, PLL_APLL, RK2928_PLL_CON(0),
582 case PLL_APLL: in rk322x_clk_get_rate()
643 case PLL_APLL: in rk322x_clk_set_rate()
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| H A D | clk_rk3328.c | 90 RK3328_CLK_DUMP(PLL_APLL, "apll", true),
106 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3328_PLL_CON(0),
800 case PLL_APLL: in rk3328_clk_get_rate()
873 case PLL_APLL: in rk3328_clk_set_rate()
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| H A D | clk_rk3066.c | 48 RK3066_CLK_DUMP(PLL_APLL, "apll", true),
513 case PLL_APLL: in rk3066_clk_set_rate()
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| H A D | clk_rk3188.c | 49 RK3188_CLK_DUMP(PLL_APLL, "apll", true),
548 case PLL_APLL: in rk3188_clk_set_rate()
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| H A D | clk_rk1808.c | 58 RK1808_CLK_DUMP(PLL_APLL, "apll", true),
80 [APLL] = PLL(pll_rk3036, PLL_APLL, RK1808_PLL_CON(0),
913 case PLL_APLL: in rk1808_clk_get_rate()
998 case PLL_APLL: in rk1808_clk_set_rate()
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| H A D | clk_rv1106.c | 39 [APLL] = PLL(pll_rk3328, PLL_APLL, RV1106_PLL_CON(0),
60 RV1106_CLK_DUMP(PLL_APLL, "apll", true),
1051 case PLL_APLL: in rv1106_clk_get_rate()
1156 case PLL_APLL: in rv1106_clk_set_rate()
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| H A D | clk_rk3308.c | 61 RK3308_CLK_DUMP(PLL_APLL, "apll"),
76 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
937 case PLL_APLL: in rk3308_clk_get_rate()
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| H A D | clk_rk3528.c | 66 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
123 RK3528_CLK_DUMP(PLL_APLL, "apll"),
1344 case PLL_APLL: in rk3528_clk_get_rate()
1462 case PLL_APLL: in rk3528_clk_set_rate()
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| H A D | clk_rk3562.c | 47 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3562_PLL_CON(0),
89 RK3562_CLK_DUMP(PLL_APLL, "apll"),
1365 case PLL_APLL: in rk3562_clk_get_rate()
1491 case PLL_APLL: in rk3562_clk_set_rate()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3288/ |
| H A D | rk3288.c | 269 clk.id = PLL_APLL; in veyron_init()
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