clk: rockchip: rv1108: Make clock ids consistent with kernel

Change-Id: Idd295c633dffbe2ed6c3f5b6e115b0fd5b040251
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

rockchip: clk: rv1108: Add some frequency setting interfaces

support PLL freq setting,
support bus and peri clk freq setting,
support aclk vio and dclk vop freq setting.

Change-Id: I894552c1e1bb1bd

rockchip: clk: rv1108: Add some frequency setting interfaces

support PLL freq setting,
support bus and peri clk freq setting,
support aclk vio and dclk vop freq setting.

Change-Id: I894552c1e1bb1bd13a143e200edf289234a53c1d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

show more ...

rockchip: clk: Add rv1108 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Change-Id: I1f

rockchip: clk: Add rv1108 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Change-Id: I1ff152b72a75680601f22c5b621de8b2198a6778
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit 2e4ce50d1aca35d13944f48a7e15d0b63e86eb38)

show more ...

Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixe

Merge git://git.denx.de/u-boot-rockchip

Here is additional rk3368 and rk3399 support, rv1108 support,
refactoring HDMI video (brought in from Anatolij's tree to resolve
conflicts), some mkimage fixes and a few other things.

show more ...

rockchip: clk: Add rv1108 clock driver

Add clock driver support for Rockchip rv1108 soc

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>