1b36e944aSJoseph Chen /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2c6f7c1a3SJoseph Chen /* 3c6f7c1a3SJoseph Chen * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4c6f7c1a3SJoseph Chen * Author: Joseph Chen <chenjh@rock-chips.com> 5c6f7c1a3SJoseph Chen */ 6c6f7c1a3SJoseph Chen 7c6f7c1a3SJoseph Chen #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 8c6f7c1a3SJoseph Chen #define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H 9c6f7c1a3SJoseph Chen 10c6f7c1a3SJoseph Chen /* cru-clocks indices */ 11c6f7c1a3SJoseph Chen 12c6f7c1a3SJoseph Chen /* core clocks */ 13c6f7c1a3SJoseph Chen #define PLL_APLL 1 14c6f7c1a3SJoseph Chen #define PLL_CPLL 2 15c6f7c1a3SJoseph Chen #define PLL_GPLL 3 16c6f7c1a3SJoseph Chen #define PLL_PPLL 4 17c6f7c1a3SJoseph Chen #define PLL_DPLL 5 18c6f7c1a3SJoseph Chen #define ARMCLK 6 19c6f7c1a3SJoseph Chen 20c6f7c1a3SJoseph Chen #define XIN_OSC0_HALF 8 21c6f7c1a3SJoseph Chen #define CLK_MATRIX_50M_SRC 9 22c6f7c1a3SJoseph Chen #define CLK_MATRIX_100M_SRC 10 23c6f7c1a3SJoseph Chen #define CLK_MATRIX_150M_SRC 11 24c6f7c1a3SJoseph Chen #define CLK_MATRIX_200M_SRC 12 25c6f7c1a3SJoseph Chen #define CLK_MATRIX_250M_SRC 13 26c6f7c1a3SJoseph Chen #define CLK_MATRIX_300M_SRC 14 27c6f7c1a3SJoseph Chen #define CLK_MATRIX_339M_SRC 15 28c6f7c1a3SJoseph Chen #define CLK_MATRIX_400M_SRC 16 29c6f7c1a3SJoseph Chen #define CLK_MATRIX_500M_SRC 17 30c6f7c1a3SJoseph Chen #define CLK_MATRIX_600M_SRC 18 31c6f7c1a3SJoseph Chen #define CLK_UART0_SRC 19 32c6f7c1a3SJoseph Chen #define CLK_UART0_FRAC 20 33c6f7c1a3SJoseph Chen #define SCLK_UART0 21 34c6f7c1a3SJoseph Chen #define CLK_UART1_SRC 22 35c6f7c1a3SJoseph Chen #define CLK_UART1_FRAC 23 36c6f7c1a3SJoseph Chen #define SCLK_UART1 24 37c6f7c1a3SJoseph Chen #define CLK_UART2_SRC 25 38c6f7c1a3SJoseph Chen #define CLK_UART2_FRAC 26 39c6f7c1a3SJoseph Chen #define SCLK_UART2 27 40c6f7c1a3SJoseph Chen #define CLK_UART3_SRC 28 41c6f7c1a3SJoseph Chen #define CLK_UART3_FRAC 29 42c6f7c1a3SJoseph Chen #define SCLK_UART3 30 43c6f7c1a3SJoseph Chen #define CLK_UART4_SRC 31 44c6f7c1a3SJoseph Chen #define CLK_UART4_FRAC 32 45c6f7c1a3SJoseph Chen #define SCLK_UART4 33 46c6f7c1a3SJoseph Chen #define CLK_UART5_SRC 34 47c6f7c1a3SJoseph Chen #define CLK_UART5_FRAC 35 48c6f7c1a3SJoseph Chen #define SCLK_UART5 36 49c6f7c1a3SJoseph Chen #define CLK_UART6_SRC 37 50c6f7c1a3SJoseph Chen #define CLK_UART6_FRAC 38 51c6f7c1a3SJoseph Chen #define SCLK_UART6 39 52c6f7c1a3SJoseph Chen #define CLK_UART7_SRC 40 53c6f7c1a3SJoseph Chen #define CLK_UART7_FRAC 41 54c6f7c1a3SJoseph Chen #define SCLK_UART7 42 55c6f7c1a3SJoseph Chen #define CLK_I2S0_2CH_SRC 43 56c6f7c1a3SJoseph Chen #define CLK_I2S0_2CH_FRAC 44 57c6f7c1a3SJoseph Chen #define MCLK_I2S0_2CH_SAI_SRC 45 58c6f7c1a3SJoseph Chen #define CLK_I2S3_8CH_SRC 46 59c6f7c1a3SJoseph Chen #define CLK_I2S3_8CH_FRAC 47 60c6f7c1a3SJoseph Chen #define MCLK_I2S3_8CH_SAI_SRC 48 61c6f7c1a3SJoseph Chen #define CLK_I2S1_8CH_SRC 49 62c6f7c1a3SJoseph Chen #define CLK_I2S1_8CH_FRAC 50 63c6f7c1a3SJoseph Chen #define MCLK_I2S1_8CH_SAI_SRC 51 64c6f7c1a3SJoseph Chen #define CLK_I2S2_2CH_SRC 52 65c6f7c1a3SJoseph Chen #define CLK_I2S2_2CH_FRAC 53 66c6f7c1a3SJoseph Chen #define MCLK_I2S2_2CH_SAI_SRC 54 67c6f7c1a3SJoseph Chen #define CLK_SPDIF_SRC 55 68c6f7c1a3SJoseph Chen #define CLK_SPDIF_FRAC 56 69c6f7c1a3SJoseph Chen #define MCLK_SPDIF_SRC 57 70c6f7c1a3SJoseph Chen #define DCLK_VOP_SRC0 58 71c6f7c1a3SJoseph Chen #define DCLK_VOP_SRC1 59 72c6f7c1a3SJoseph Chen #define CLK_HSM 60 73c6f7c1a3SJoseph Chen #define CLK_CORE_SRC_ACS 63 74c6f7c1a3SJoseph Chen #define CLK_CORE_SRC_PVTMUX 65 75c6f7c1a3SJoseph Chen #define CLK_CORE_SRC 66 76c6f7c1a3SJoseph Chen #define CLK_CORE 67 77c6f7c1a3SJoseph Chen #define ACLK_M_CORE_BIU 68 78c6f7c1a3SJoseph Chen #define CLK_CORE_PVTPLL_SRC 69 79c6f7c1a3SJoseph Chen #define PCLK_DBG 70 80c6f7c1a3SJoseph Chen #define SWCLKTCK 71 81c6f7c1a3SJoseph Chen #define CLK_SCANHS_CORE 72 82c6f7c1a3SJoseph Chen #define CLK_SCANHS_ACLKM_CORE 73 83c6f7c1a3SJoseph Chen #define CLK_SCANHS_PCLK_DBG 74 84c6f7c1a3SJoseph Chen #define CLK_SCANHS_PCLK_CPU_BIU 76 85c6f7c1a3SJoseph Chen #define PCLK_CPU_ROOT 77 86c6f7c1a3SJoseph Chen #define PCLK_CORE_GRF 78 87c6f7c1a3SJoseph Chen #define PCLK_DAPLITE_BIU 79 88c6f7c1a3SJoseph Chen #define PCLK_CPU_BIU 80 89c6f7c1a3SJoseph Chen #define CLK_REF_PVTPLL_CORE 81 90c6f7c1a3SJoseph Chen #define ACLK_BUS_VOPGL_ROOT 85 91c6f7c1a3SJoseph Chen #define ACLK_BUS_VOPGL_BIU 86 92c6f7c1a3SJoseph Chen #define ACLK_BUS_H_ROOT 87 93c6f7c1a3SJoseph Chen #define ACLK_BUS_H_BIU 88 94c6f7c1a3SJoseph Chen #define ACLK_BUS_ROOT 89 95c6f7c1a3SJoseph Chen #define HCLK_BUS_ROOT 90 96c6f7c1a3SJoseph Chen #define PCLK_BUS_ROOT 91 97c6f7c1a3SJoseph Chen #define ACLK_BUS_M_ROOT 92 98c6f7c1a3SJoseph Chen #define ACLK_SYSMEM_BIU 93 99c6f7c1a3SJoseph Chen #define CLK_TIMER_ROOT 95 100c6f7c1a3SJoseph Chen #define ACLK_BUS_BIU 96 101c6f7c1a3SJoseph Chen #define HCLK_BUS_BIU 97 102c6f7c1a3SJoseph Chen #define PCLK_BUS_BIU 98 103c6f7c1a3SJoseph Chen #define PCLK_DFT2APB 99 104c6f7c1a3SJoseph Chen #define PCLK_BUS_GRF 100 105c6f7c1a3SJoseph Chen #define ACLK_BUS_M_BIU 101 106c6f7c1a3SJoseph Chen #define ACLK_GIC 102 107c6f7c1a3SJoseph Chen #define ACLK_SPINLOCK 103 108c6f7c1a3SJoseph Chen #define ACLK_DMAC 104 109c6f7c1a3SJoseph Chen #define PCLK_TIMER 105 110c6f7c1a3SJoseph Chen #define CLK_TIMER0 106 111c6f7c1a3SJoseph Chen #define CLK_TIMER1 107 112c6f7c1a3SJoseph Chen #define CLK_TIMER2 108 113c6f7c1a3SJoseph Chen #define CLK_TIMER3 109 114c6f7c1a3SJoseph Chen #define CLK_TIMER4 110 115c6f7c1a3SJoseph Chen #define CLK_TIMER5 111 116c6f7c1a3SJoseph Chen #define PCLK_JDBCK_DAP 112 117c6f7c1a3SJoseph Chen #define CLK_JDBCK_DAP 113 118c6f7c1a3SJoseph Chen #define PCLK_WDT_NS 114 119c6f7c1a3SJoseph Chen #define TCLK_WDT_NS 115 120c6f7c1a3SJoseph Chen #define HCLK_TRNG_NS 116 121c6f7c1a3SJoseph Chen #define PCLK_UART0 117 122c6f7c1a3SJoseph Chen #define CLK_CORE_CRYPTO 119 123c6f7c1a3SJoseph Chen #define CLK_PKA_CRYPTO 120 124c6f7c1a3SJoseph Chen #define ACLK_CRYPTO 121 125c6f7c1a3SJoseph Chen #define HCLK_CRYPTO 122 126c6f7c1a3SJoseph Chen #define PCLK_DMA2DDR 123 127c6f7c1a3SJoseph Chen #define ACLK_DMA2DDR 124 128c6f7c1a3SJoseph Chen #define PCLK_PWM0 126 129c6f7c1a3SJoseph Chen #define CLK_PWM0 127 130c6f7c1a3SJoseph Chen #define CLK_CAPTURE_PWM0 128 131c6f7c1a3SJoseph Chen #define PCLK_PWM1 129 132c6f7c1a3SJoseph Chen #define CLK_PWM1 130 133c6f7c1a3SJoseph Chen #define CLK_CAPTURE_PWM1 131 134c6f7c1a3SJoseph Chen #define PCLK_SCR 134 135c6f7c1a3SJoseph Chen #define ACLK_DCF 135 136c6f7c1a3SJoseph Chen #define PCLK_INTMUX 138 137c6f7c1a3SJoseph Chen #define CLK_PPLL_I 141 138c6f7c1a3SJoseph Chen #define CLK_PPLL_MUX 142 139c6f7c1a3SJoseph Chen #define CLK_PPLL_100M_MATRIX 143 140c6f7c1a3SJoseph Chen #define CLK_PPLL_50M_MATRIX 144 141c6f7c1a3SJoseph Chen #define CLK_REF_PCIE_INNER_PHY 145 142c6f7c1a3SJoseph Chen #define CLK_REF_PCIE_100M_PHY 146 143c6f7c1a3SJoseph Chen #define ACLK_VPU_L_ROOT 147 144c6f7c1a3SJoseph Chen #define CLK_GMAC1_VPU_25M 148 145c6f7c1a3SJoseph Chen #define CLK_PPLL_125M_MATRIX 149 146c6f7c1a3SJoseph Chen #define ACLK_VPU_ROOT 150 147c6f7c1a3SJoseph Chen #define HCLK_VPU_ROOT 151 148c6f7c1a3SJoseph Chen #define PCLK_VPU_ROOT 152 149c6f7c1a3SJoseph Chen #define ACLK_VPU_BIU 153 150c6f7c1a3SJoseph Chen #define HCLK_VPU_BIU 154 151c6f7c1a3SJoseph Chen #define PCLK_VPU_BIU 155 152c6f7c1a3SJoseph Chen #define ACLK_VPU 156 153c6f7c1a3SJoseph Chen #define HCLK_VPU 157 154c6f7c1a3SJoseph Chen #define PCLK_CRU_PCIE 158 155c6f7c1a3SJoseph Chen #define PCLK_VPU_GRF 159 156c6f7c1a3SJoseph Chen #define HCLK_SFC 160 157c6f7c1a3SJoseph Chen #define SCLK_SFC 161 158c6f7c1a3SJoseph Chen #define CCLK_SRC_EMMC 163 159c6f7c1a3SJoseph Chen #define HCLK_EMMC 164 160c6f7c1a3SJoseph Chen #define ACLK_EMMC 165 161c6f7c1a3SJoseph Chen #define BCLK_EMMC 166 162c6f7c1a3SJoseph Chen #define TCLK_EMMC 167 163c6f7c1a3SJoseph Chen #define PCLK_GPIO1 168 164c6f7c1a3SJoseph Chen #define DBCLK_GPIO1 169 165c6f7c1a3SJoseph Chen #define ACLK_VPU_L_BIU 172 166c6f7c1a3SJoseph Chen #define PCLK_VPU_IOC 173 167c6f7c1a3SJoseph Chen #define HCLK_SAI_I2S0 174 168c6f7c1a3SJoseph Chen #define MCLK_SAI_I2S0 175 169c6f7c1a3SJoseph Chen #define HCLK_SAI_I2S2 176 170c6f7c1a3SJoseph Chen #define MCLK_SAI_I2S2 177 171c6f7c1a3SJoseph Chen #define PCLK_ACODEC 178 172c6f7c1a3SJoseph Chen #define MCLK_ACODEC_TX 179 173c6f7c1a3SJoseph Chen #define PCLK_GPIO3 186 174c6f7c1a3SJoseph Chen #define DBCLK_GPIO3 187 175c6f7c1a3SJoseph Chen #define PCLK_SPI1 189 176c6f7c1a3SJoseph Chen #define CLK_SPI1 190 177c6f7c1a3SJoseph Chen #define SCLK_IN_SPI1 191 178c6f7c1a3SJoseph Chen #define PCLK_UART2 192 179c6f7c1a3SJoseph Chen #define PCLK_UART5 194 180c6f7c1a3SJoseph Chen #define PCLK_UART6 196 181c6f7c1a3SJoseph Chen #define PCLK_UART7 198 182c6f7c1a3SJoseph Chen #define PCLK_I2C3 200 183c6f7c1a3SJoseph Chen #define CLK_I2C3 201 184c6f7c1a3SJoseph Chen #define PCLK_I2C5 202 185c6f7c1a3SJoseph Chen #define CLK_I2C5 203 186c6f7c1a3SJoseph Chen #define PCLK_I2C6 204 187c6f7c1a3SJoseph Chen #define CLK_I2C6 205 188c6f7c1a3SJoseph Chen #define ACLK_MAC_VPU 206 189c6f7c1a3SJoseph Chen #define PCLK_MAC_VPU 207 190c6f7c1a3SJoseph Chen #define CLK_GMAC1_RMII_VPU 209 191c6f7c1a3SJoseph Chen #define CLK_GMAC1_SRC_VPU 210 192c6f7c1a3SJoseph Chen #define PCLK_PCIE 215 193c6f7c1a3SJoseph Chen #define CLK_PCIE_AUX 216 194c6f7c1a3SJoseph Chen #define ACLK_PCIE 217 195c6f7c1a3SJoseph Chen #define HCLK_PCIE_SLV 218 196c6f7c1a3SJoseph Chen #define HCLK_PCIE_DBI 219 197c6f7c1a3SJoseph Chen #define PCLK_PCIE_PHY 220 198c6f7c1a3SJoseph Chen #define PCLK_PIPE_GRF 221 199c6f7c1a3SJoseph Chen #define CLK_PIPE_USB3OTG_COMBO 230 200c6f7c1a3SJoseph Chen #define CLK_UTMI_USB3OTG 232 201c6f7c1a3SJoseph Chen #define CLK_PCIE_PIPE_PHY 235 202c6f7c1a3SJoseph Chen #define CCLK_SRC_SDIO0 240 203c6f7c1a3SJoseph Chen #define HCLK_SDIO0 241 204c6f7c1a3SJoseph Chen #define CCLK_SRC_SDIO1 244 205c6f7c1a3SJoseph Chen #define HCLK_SDIO1 245 206c6f7c1a3SJoseph Chen #define CLK_TS_0 246 207c6f7c1a3SJoseph Chen #define CLK_TS_1 247 208c6f7c1a3SJoseph Chen #define PCLK_CAN2 250 209c6f7c1a3SJoseph Chen #define CLK_CAN2 251 210c6f7c1a3SJoseph Chen #define PCLK_CAN3 252 211c6f7c1a3SJoseph Chen #define CLK_CAN3 253 212c6f7c1a3SJoseph Chen #define PCLK_SARADC 256 213c6f7c1a3SJoseph Chen #define CLK_SARADC 257 214c6f7c1a3SJoseph Chen #define PCLK_TSADC 258 215c6f7c1a3SJoseph Chen #define CLK_TSADC 259 216c6f7c1a3SJoseph Chen #define CLK_TSADC_TSEN 260 217c6f7c1a3SJoseph Chen #define ACLK_USB3OTG 261 218c6f7c1a3SJoseph Chen #define CLK_REF_USB3OTG 262 219c6f7c1a3SJoseph Chen #define CLK_SUSPEND_USB3OTG 263 220c6f7c1a3SJoseph Chen #define ACLK_GPU_ROOT 269 221c6f7c1a3SJoseph Chen #define PCLK_GPU_ROOT 270 222c6f7c1a3SJoseph Chen #define ACLK_GPU_BIU 271 223c6f7c1a3SJoseph Chen #define PCLK_GPU_BIU 272 224c6f7c1a3SJoseph Chen #define ACLK_GPU 273 225c6f7c1a3SJoseph Chen #define CLK_GPU_PVTPLL_SRC 274 226c6f7c1a3SJoseph Chen #define ACLK_GPU_MALI 275 227c6f7c1a3SJoseph Chen #define HCLK_RKVENC_ROOT 281 228c6f7c1a3SJoseph Chen #define ACLK_RKVENC_ROOT 282 229c6f7c1a3SJoseph Chen #define PCLK_RKVENC_ROOT 283 230c6f7c1a3SJoseph Chen #define HCLK_RKVENC_BIU 284 231c6f7c1a3SJoseph Chen #define ACLK_RKVENC_BIU 285 232c6f7c1a3SJoseph Chen #define PCLK_RKVENC_BIU 286 233c6f7c1a3SJoseph Chen #define HCLK_RKVENC 287 234c6f7c1a3SJoseph Chen #define ACLK_RKVENC 288 235c6f7c1a3SJoseph Chen #define CLK_CORE_RKVENC 289 236c6f7c1a3SJoseph Chen #define HCLK_SAI_I2S1 290 237c6f7c1a3SJoseph Chen #define MCLK_SAI_I2S1 291 238c6f7c1a3SJoseph Chen #define PCLK_I2C1 292 239c6f7c1a3SJoseph Chen #define CLK_I2C1 293 240c6f7c1a3SJoseph Chen #define PCLK_I2C0 294 241c6f7c1a3SJoseph Chen #define CLK_I2C0 295 242c6f7c1a3SJoseph Chen #define CLK_UART_JTAG 296 243c6f7c1a3SJoseph Chen #define PCLK_SPI0 297 244c6f7c1a3SJoseph Chen #define CLK_SPI0 298 245c6f7c1a3SJoseph Chen #define SCLK_IN_SPI0 299 246c6f7c1a3SJoseph Chen #define PCLK_GPIO4 300 247c6f7c1a3SJoseph Chen #define DBCLK_GPIO4 301 248c6f7c1a3SJoseph Chen #define PCLK_RKVENC_IOC 302 249c6f7c1a3SJoseph Chen #define HCLK_SPDIF 308 250c6f7c1a3SJoseph Chen #define MCLK_SPDIF 309 251c6f7c1a3SJoseph Chen #define HCLK_PDM 310 252c6f7c1a3SJoseph Chen #define MCLK_PDM 311 253c6f7c1a3SJoseph Chen #define PCLK_UART1 315 254c6f7c1a3SJoseph Chen #define PCLK_UART3 317 255c6f7c1a3SJoseph Chen #define PCLK_RKVENC_GRF 319 256c6f7c1a3SJoseph Chen #define PCLK_CAN0 320 257c6f7c1a3SJoseph Chen #define CLK_CAN0 321 258c6f7c1a3SJoseph Chen #define PCLK_CAN1 322 259c6f7c1a3SJoseph Chen #define CLK_CAN1 323 260c6f7c1a3SJoseph Chen #define ACLK_VO_ROOT 324 261c6f7c1a3SJoseph Chen #define HCLK_VO_ROOT 325 262c6f7c1a3SJoseph Chen #define PCLK_VO_ROOT 326 263c6f7c1a3SJoseph Chen #define ACLK_VO_BIU 327 264c6f7c1a3SJoseph Chen #define HCLK_VO_BIU 328 265c6f7c1a3SJoseph Chen #define PCLK_VO_BIU 329 266c6f7c1a3SJoseph Chen #define HCLK_RGA2E 330 267c6f7c1a3SJoseph Chen #define ACLK_RGA2E 331 268c6f7c1a3SJoseph Chen #define CLK_CORE_RGA2E 332 269c6f7c1a3SJoseph Chen #define HCLK_VDPP 333 270c6f7c1a3SJoseph Chen #define ACLK_VDPP 334 271c6f7c1a3SJoseph Chen #define CLK_CORE_VDPP 335 272c6f7c1a3SJoseph Chen #define PCLK_VO_GRF 336 273c6f7c1a3SJoseph Chen #define PCLK_CRU 337 274c6f7c1a3SJoseph Chen #define ACLK_VOP_ROOT 338 275c6f7c1a3SJoseph Chen #define ACLK_VOP_BIU 339 276c6f7c1a3SJoseph Chen #define HCLK_VOP 340 277c6f7c1a3SJoseph Chen #define DCLK_VOP0 341 278c6f7c1a3SJoseph Chen #define DCLK_VOP1 342 279c6f7c1a3SJoseph Chen #define ACLK_VOP 343 280c6f7c1a3SJoseph Chen #define PCLK_HDMI 344 281c6f7c1a3SJoseph Chen #define CLK_SFR_HDMI 345 282c6f7c1a3SJoseph Chen #define CLK_CEC_HDMI 346 283c6f7c1a3SJoseph Chen #define CLK_SPDIF_HDMI 347 284c6f7c1a3SJoseph Chen #define CLK_HDMIPHY_TMDSSRC 348 285c6f7c1a3SJoseph Chen #define CLK_HDMIPHY_PREP 349 286c6f7c1a3SJoseph Chen #define PCLK_HDMIPHY 352 287c6f7c1a3SJoseph Chen #define HCLK_HDCP_KEY 354 288c6f7c1a3SJoseph Chen #define ACLK_HDCP 355 289c6f7c1a3SJoseph Chen #define HCLK_HDCP 356 290c6f7c1a3SJoseph Chen #define PCLK_HDCP 357 291c6f7c1a3SJoseph Chen #define HCLK_CVBS 358 292c6f7c1a3SJoseph Chen #define DCLK_CVBS 359 293c6f7c1a3SJoseph Chen #define DCLK_4X_CVBS 360 294c6f7c1a3SJoseph Chen #define ACLK_JPEG_DECODER 361 295c6f7c1a3SJoseph Chen #define HCLK_JPEG_DECODER 362 296c6f7c1a3SJoseph Chen #define ACLK_VO_L_ROOT 375 297c6f7c1a3SJoseph Chen #define ACLK_VO_L_BIU 376 298c6f7c1a3SJoseph Chen #define ACLK_MAC_VO 377 299c6f7c1a3SJoseph Chen #define PCLK_MAC_VO 378 300c6f7c1a3SJoseph Chen #define CLK_GMAC0_SRC 379 301c6f7c1a3SJoseph Chen #define CLK_GMAC0_RMII_50M 380 302c6f7c1a3SJoseph Chen #define CLK_GMAC0_TX 381 303c6f7c1a3SJoseph Chen #define CLK_GMAC0_RX 382 304c6f7c1a3SJoseph Chen #define ACLK_JPEG_ROOT 385 305c6f7c1a3SJoseph Chen #define ACLK_JPEG_BIU 386 306c6f7c1a3SJoseph Chen #define HCLK_SAI_I2S3 387 307c6f7c1a3SJoseph Chen #define MCLK_SAI_I2S3 388 308c6f7c1a3SJoseph Chen #define CLK_MACPHY 398 309c6f7c1a3SJoseph Chen #define PCLK_VCDCPHY 399 310c6f7c1a3SJoseph Chen #define PCLK_GPIO2 404 311c6f7c1a3SJoseph Chen #define DBCLK_GPIO2 405 312c6f7c1a3SJoseph Chen #define PCLK_VO_IOC 406 313c6f7c1a3SJoseph Chen #define CCLK_SRC_SDMMC0 407 314c6f7c1a3SJoseph Chen #define HCLK_SDMMC0 408 315c6f7c1a3SJoseph Chen #define PCLK_OTPC_NS 411 316c6f7c1a3SJoseph Chen #define CLK_SBPI_OTPC_NS 412 317c6f7c1a3SJoseph Chen #define CLK_USER_OTPC_NS 413 318c6f7c1a3SJoseph Chen #define CLK_HDMIHDP0 415 319c6f7c1a3SJoseph Chen #define HCLK_USBHOST 416 320c6f7c1a3SJoseph Chen #define HCLK_USBHOST_ARB 417 321c6f7c1a3SJoseph Chen #define CLK_USBHOST_OHCI 418 322c6f7c1a3SJoseph Chen #define CLK_USBHOST_UTMI 419 323c6f7c1a3SJoseph Chen #define PCLK_UART4 420 324c6f7c1a3SJoseph Chen #define PCLK_I2C4 422 325c6f7c1a3SJoseph Chen #define CLK_I2C4 423 326c6f7c1a3SJoseph Chen #define PCLK_I2C7 424 327c6f7c1a3SJoseph Chen #define CLK_I2C7 425 328c6f7c1a3SJoseph Chen #define PCLK_USBPHY 426 329c6f7c1a3SJoseph Chen #define CLK_REF_USBPHY 427 330c6f7c1a3SJoseph Chen #define HCLK_RKVDEC_ROOT 433 331c6f7c1a3SJoseph Chen #define ACLK_RKVDEC_ROOT_NDFT 434 332c6f7c1a3SJoseph Chen #define PCLK_DDRPHY_CRU 435 333c6f7c1a3SJoseph Chen #define HCLK_RKVDEC_BIU 436 334c6f7c1a3SJoseph Chen #define ACLK_RKVDEC_BIU 437 335c6f7c1a3SJoseph Chen #define ACLK_RKVDEC 439 336c6f7c1a3SJoseph Chen #define HCLK_RKVDEC 440 337c6f7c1a3SJoseph Chen #define CLK_HEVC_CA_RKVDEC 441 338c6f7c1a3SJoseph Chen #define ACLK_RKVDEC_PVTMUX_ROOT 442 339c6f7c1a3SJoseph Chen #define CLK_RKVDEC_PVTPLL_SRC 443 340c6f7c1a3SJoseph Chen #define PCLK_DDR_ROOT 449 341c6f7c1a3SJoseph Chen #define PCLK_DDR_BIU 450 342c6f7c1a3SJoseph Chen #define PCLK_DDRC 451 343c6f7c1a3SJoseph Chen #define PCLK_DDRMON 452 344c6f7c1a3SJoseph Chen #define CLK_TIMER_DDRMON 453 345c6f7c1a3SJoseph Chen #define PCLK_MSCH_BIU 454 346c6f7c1a3SJoseph Chen #define PCLK_DDR_GRF 455 347c6f7c1a3SJoseph Chen #define PCLK_DDR_HWLP 456 348c6f7c1a3SJoseph Chen #define PCLK_DDRPHY 457 349c6f7c1a3SJoseph Chen #define CLK_MSCH_BIU 463 350c6f7c1a3SJoseph Chen #define ACLK_DDR_UPCTL 464 351c6f7c1a3SJoseph Chen #define CLK_DDR_UPCTL 465 352c6f7c1a3SJoseph Chen #define CLK_DDRMON 466 353c6f7c1a3SJoseph Chen #define ACLK_DDR_SCRAMBLE 467 354c6f7c1a3SJoseph Chen #define ACLK_SPLIT 468 355c6f7c1a3SJoseph Chen #define CLK_DDRC_SRC 470 356c6f7c1a3SJoseph Chen #define CLK_DDR_PHY 471 357c6f7c1a3SJoseph Chen #define PCLK_OTPC_S 472 358c6f7c1a3SJoseph Chen #define CLK_SBPI_OTPC_S 473 359c6f7c1a3SJoseph Chen #define CLK_USER_OTPC_S 474 360c6f7c1a3SJoseph Chen #define PCLK_KEYREADER 475 361c6f7c1a3SJoseph Chen #define PCLK_BUS_SGRF 476 362c6f7c1a3SJoseph Chen #define PCLK_STIMER 477 363c6f7c1a3SJoseph Chen #define CLK_STIMER0 478 364c6f7c1a3SJoseph Chen #define CLK_STIMER1 479 365c6f7c1a3SJoseph Chen #define PCLK_WDT_S 480 366c6f7c1a3SJoseph Chen #define TCLK_WDT_S 481 367c6f7c1a3SJoseph Chen #define HCLK_TRNG_S 482 368c6f7c1a3SJoseph Chen #define PCLK_KLAD 483 369c6f7c1a3SJoseph Chen #define HCLK_CRYPTO_S 484 370c6f7c1a3SJoseph Chen #define HCLK_KLAD 485 371c6f7c1a3SJoseph Chen #define HCLK_BOOTROM 486 372c6f7c1a3SJoseph Chen #define PCLK_DCF 487 373c6f7c1a3SJoseph Chen #define ACLK_SYSMEM 488 374c6f7c1a3SJoseph Chen #define HCLK_TSP 489 375c6f7c1a3SJoseph Chen #define ACLK_TSP 490 376c6f7c1a3SJoseph Chen #define CLK_CORE_TSP 491 377c6f7c1a3SJoseph Chen #define CLK_OTPC_ARB 492 378c6f7c1a3SJoseph Chen #define PCLK_OTP_MASK 493 379c6f7c1a3SJoseph Chen #define CLK_PMC_OTP 494 380c6f7c1a3SJoseph Chen #define PCLK_PMU_ROOT 495 381c6f7c1a3SJoseph Chen #define HCLK_PMU_ROOT 496 382c6f7c1a3SJoseph Chen #define PCLK_I2C2 497 383c6f7c1a3SJoseph Chen #define CLK_I2C2 498 384c6f7c1a3SJoseph Chen #define HCLK_PMU_BIU 500 385c6f7c1a3SJoseph Chen #define PCLK_PMU_BIU 501 386c6f7c1a3SJoseph Chen #define FCLK_MCU 502 387c6f7c1a3SJoseph Chen #define RTC_CLK_MCU 504 388c6f7c1a3SJoseph Chen #define PCLK_OSCCHK 505 389c6f7c1a3SJoseph Chen #define CLK_PMU_MCU_JTAG 506 390c6f7c1a3SJoseph Chen #define PCLK_PMU 508 391c6f7c1a3SJoseph Chen #define PCLK_GPIO0 509 392c6f7c1a3SJoseph Chen #define DBCLK_GPIO0 510 393c6f7c1a3SJoseph Chen #define XIN_OSC0_DIV 511 394c6f7c1a3SJoseph Chen #define CLK_DEEPSLOW 512 395c6f7c1a3SJoseph Chen #define CLK_DDR_FAIL_SAFE 513 396c6f7c1a3SJoseph Chen #define PCLK_PMU_HP_TIMER 514 397b36e944aSJoseph Chen #define CLK_PMU_HP_TIMER 515 398c6f7c1a3SJoseph Chen #define CLK_PMU_32K_HP_TIMER 516 399c6f7c1a3SJoseph Chen #define PCLK_PMU_IOC 517 400c6f7c1a3SJoseph Chen #define PCLK_PMU_CRU 518 401c6f7c1a3SJoseph Chen #define PCLK_PMU_GRF 519 402c6f7c1a3SJoseph Chen #define PCLK_PMU_WDT 520 403c6f7c1a3SJoseph Chen #define TCLK_PMU_WDT 521 404c6f7c1a3SJoseph Chen #define PCLK_PMU_MAILBOX 522 405c6f7c1a3SJoseph Chen #define PCLK_SCRKEYGEN 524 406c6f7c1a3SJoseph Chen #define CLK_SCRKEYGEN 525 407c6f7c1a3SJoseph Chen #define CLK_PVTM_OSCCHK 526 408c6f7c1a3SJoseph Chen #define CLK_REFOUT 530 409c6f7c1a3SJoseph Chen #define CLK_PVTM_PMU 532 410c6f7c1a3SJoseph Chen #define PCLK_PVTM_PMU 533 411c6f7c1a3SJoseph Chen #define PCLK_PMU_SGRF 534 412c6f7c1a3SJoseph Chen #define HCLK_PMU_SRAM 535 413c6f7c1a3SJoseph Chen #define CLK_UART0 536 414c6f7c1a3SJoseph Chen #define CLK_UART1 537 415c6f7c1a3SJoseph Chen #define CLK_UART2 538 416c6f7c1a3SJoseph Chen #define CLK_UART3 539 417c6f7c1a3SJoseph Chen #define CLK_UART4 540 418c6f7c1a3SJoseph Chen #define CLK_UART5 541 419c6f7c1a3SJoseph Chen #define CLK_UART6 542 420c6f7c1a3SJoseph Chen #define CLK_UART7 543 421c6f7c1a3SJoseph Chen #define MCLK_I2S0_2CH_SAI_SRC_PRE 544 422c6f7c1a3SJoseph Chen #define MCLK_I2S1_8CH_SAI_SRC_PRE 545 423c6f7c1a3SJoseph Chen #define MCLK_I2S2_2CH_SAI_SRC_PRE 546 424c6f7c1a3SJoseph Chen #define MCLK_I2S3_8CH_SAI_SRC_PRE 547 425c6f7c1a3SJoseph Chen #define MCLK_SDPDIF_SRC_PRE 548 426c6f7c1a3SJoseph Chen #define CLK_NR_CLKS (MCLK_SDPDIF_SRC_PRE + 1) 427c6f7c1a3SJoseph Chen 428c6f7c1a3SJoseph Chen /* grf-clocks indices */ 429c6f7c1a3SJoseph Chen #define SCLK_SDMMC_DRV 1 430c6f7c1a3SJoseph Chen #define SCLK_SDMMC_SAMPLE 2 431c6f7c1a3SJoseph Chen #define SCLK_SDIO0_DRV 3 432c6f7c1a3SJoseph Chen #define SCLK_SDIO0_SAMPLE 4 433c6f7c1a3SJoseph Chen #define SCLK_SDIO1_DRV 5 434c6f7c1a3SJoseph Chen #define SCLK_SDIO1_SAMPLE 6 435c6f7c1a3SJoseph Chen #define CLK_NR_GRF_CLKS (SCLK_SDIO1_SAMPLE + 1) 436c6f7c1a3SJoseph Chen 437c6f7c1a3SJoseph Chen /* scmi-clocks indices */ 438c6f7c1a3SJoseph Chen #define SCMI_PCLK_KEYREADER 0 439c6f7c1a3SJoseph Chen #define SCMI_HCLK_KLAD 1 440c6f7c1a3SJoseph Chen #define SCMI_PCLK_KLAD 2 441c6f7c1a3SJoseph Chen #define SCMI_HCLK_TRNG_S 3 442c6f7c1a3SJoseph Chen #define SCMI_HCLK_CRYPTO_S 4 443c6f7c1a3SJoseph Chen #define SCMI_PCLK_WDT_S 5 444c6f7c1a3SJoseph Chen #define SCMI_TCLK_WDT_S 6 445c6f7c1a3SJoseph Chen #define SCMI_PCLK_STIMER 7 446c6f7c1a3SJoseph Chen #define SCMI_CLK_STIMER0 8 447c6f7c1a3SJoseph Chen #define SCMI_CLK_STIMER1 9 448c6f7c1a3SJoseph Chen #define SCMI_PCLK_OTP_MASK 10 449c6f7c1a3SJoseph Chen #define SCMI_PCLK_OTPC_S 11 450c6f7c1a3SJoseph Chen #define SCMI_CLK_SBPI_OTPC_S 12 451c6f7c1a3SJoseph Chen #define SCMI_CLK_USER_OTPC_S 13 452c6f7c1a3SJoseph Chen #define SCMI_CLK_PMC_OTP 14 453c6f7c1a3SJoseph Chen #define SCMI_CLK_OTPC_ARB 15 454c6f7c1a3SJoseph Chen #define SCMI_CLK_CORE_TSP 16 455c6f7c1a3SJoseph Chen #define SCMI_ACLK_TSP 17 456c6f7c1a3SJoseph Chen #define SCMI_HCLK_TSP 18 457c6f7c1a3SJoseph Chen #define SCMI_PCLK_DCF 19 458b36e944aSJoseph Chen #define SCMI_CLK_DDR 20 459b36e944aSJoseph Chen #define SCMI_CLK_CPU 21 460b36e944aSJoseph Chen #define SCMI_CLK_GPU 22 4613e68d308SJoseph Chen #define SCMI_CORE_CRYPTO 23 4623e68d308SJoseph Chen #define SCMI_ACLK_CRYPTO 24 4633e68d308SJoseph Chen #define SCMI_PKA_CRYPTO 25 4643e68d308SJoseph Chen #define SCMI_HCLK_CRYPTO 26 4653e68d308SJoseph Chen #define SCMI_CORE_CRYPTO_S 27 4663e68d308SJoseph Chen #define SCMI_ACLK_CRYPTO_S 28 4673e68d308SJoseph Chen #define SCMI_PKA_CRYPTO_S 29 4683e68d308SJoseph Chen #define SCMI_CORE_KLAD 30 4693e68d308SJoseph Chen #define SCMI_ACLK_KLAD 31 470*4c7992e5SJoseph Chen #define SCMI_HCLK_TRNG 32 471c6f7c1a3SJoseph Chen 472c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON03(Offset:0xA0C) 473c6f7c1a3SJoseph Chen #define SRST_NCOREPORESET0 0x00000030 474c6f7c1a3SJoseph Chen #define SRST_NCOREPORESET1 0x00000031 475c6f7c1a3SJoseph Chen #define SRST_NCOREPORESET2 0x00000032 476c6f7c1a3SJoseph Chen #define SRST_NCOREPORESET3 0x00000033 477c6f7c1a3SJoseph Chen #define SRST_NCORESET0 0x00000034 478c6f7c1a3SJoseph Chen #define SRST_NCORESET1 0x00000035 479c6f7c1a3SJoseph Chen #define SRST_NCORESET2 0x00000036 480c6f7c1a3SJoseph Chen #define SRST_NCORESET3 0x00000037 481c6f7c1a3SJoseph Chen #define SRST_NL2RESET 0x00000038 482c6f7c1a3SJoseph Chen #define SRST_ARESETN_M_CORE_BIU 0x00000039 483b36e944aSJoseph Chen #define SRST_RESETN_CORE_CRYPTO 0x0000003A 484c6f7c1a3SJoseph Chen 485c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON05(Offset:0xA14) 486c6f7c1a3SJoseph Chen #define SRST_PRESETN_DBG 0x0000005D 487c6f7c1a3SJoseph Chen #define SRST_POTRESETN_DBG 0x0000005E 488c6f7c1a3SJoseph Chen #define SRST_NTRESETN_DBG 0x0000005F 489c6f7c1a3SJoseph Chen 490c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON06(Offset:0xA18) 491c6f7c1a3SJoseph Chen #define SRST_PRESETN_CORE_GRF 0x00000062 492c6f7c1a3SJoseph Chen #define SRST_PRESETN_DAPLITE_BIU 0x00000063 493c6f7c1a3SJoseph Chen #define SRST_PRESETN_CPU_BIU 0x00000064 494c6f7c1a3SJoseph Chen #define SRST_RESETN_REF_PVTPLL_CORE 0x00000067 495c6f7c1a3SJoseph Chen 496c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON08(Offset:0xA20) 497c6f7c1a3SJoseph Chen #define SRST_ARESETN_BUS_VOPGL_BIU 0x00000081 498c6f7c1a3SJoseph Chen #define SRST_ARESETN_BUS_H_BIU 0x00000083 499c6f7c1a3SJoseph Chen #define SRST_ARESETN_SYSMEM_BIU 0x00000088 500c6f7c1a3SJoseph Chen #define SRST_ARESETN_BUS_BIU 0x0000008A 501c6f7c1a3SJoseph Chen #define SRST_HRESETN_BUS_BIU 0x0000008B 502c6f7c1a3SJoseph Chen #define SRST_PRESETN_BUS_BIU 0x0000008C 503c6f7c1a3SJoseph Chen #define SRST_PRESETN_DFT2APB 0x0000008D 504c6f7c1a3SJoseph Chen #define SRST_PRESETN_BUS_GRF 0x0000008F 505c6f7c1a3SJoseph Chen 506c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON09(Offset:0xA24) 507c6f7c1a3SJoseph Chen #define SRST_ARESETN_BUS_M_BIU 0x00000090 508c6f7c1a3SJoseph Chen #define SRST_ARESETN_GIC 0x00000091 509c6f7c1a3SJoseph Chen #define SRST_ARESETN_SPINLOCK 0x00000092 510c6f7c1a3SJoseph Chen #define SRST_ARESETN_DMAC 0x00000094 511c6f7c1a3SJoseph Chen #define SRST_PRESETN_TIMER 0x00000095 512c6f7c1a3SJoseph Chen #define SRST_RESETN_TIMER0 0x00000096 513c6f7c1a3SJoseph Chen #define SRST_RESETN_TIMER1 0x00000097 514c6f7c1a3SJoseph Chen #define SRST_RESETN_TIMER2 0x00000098 515c6f7c1a3SJoseph Chen #define SRST_RESETN_TIMER3 0x00000099 516c6f7c1a3SJoseph Chen #define SRST_RESETN_TIMER4 0x0000009A 517c6f7c1a3SJoseph Chen #define SRST_RESETN_TIMER5 0x0000009B 518c6f7c1a3SJoseph Chen #define SRST_PRESETN_JDBCK_DAP 0x0000009C 519c6f7c1a3SJoseph Chen #define SRST_RESETN_JDBCK_DAP 0x0000009D 520c6f7c1a3SJoseph Chen #define SRST_PRESETN_WDT_NS 0x0000009F 521c6f7c1a3SJoseph Chen 522c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON10(Offset:0xA28) 523c6f7c1a3SJoseph Chen #define SRST_TRESETN_WDT_NS 0x000000A0 524c6f7c1a3SJoseph Chen #define SRST_HRESETN_TRNG_NS 0x000000A3 525c6f7c1a3SJoseph Chen #define SRST_PRESETN_UART0 0x000000A7 526c6f7c1a3SJoseph Chen #define SRST_SRESETN_UART0 0x000000A8 527c6f7c1a3SJoseph Chen #define SRST_RESETN_PKA_CRYPTO 0x000000AA 528c6f7c1a3SJoseph Chen #define SRST_ARESETN_CRYPTO 0x000000AB 529c6f7c1a3SJoseph Chen #define SRST_HRESETN_CRYPTO 0x000000AC 530c6f7c1a3SJoseph Chen #define SRST_PRESETN_DMA2DDR 0x000000AD 531c6f7c1a3SJoseph Chen #define SRST_ARESETN_DMA2DDR 0x000000AE 532c6f7c1a3SJoseph Chen 533c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON11(Offset:0xA2C) 534c6f7c1a3SJoseph Chen #define SRST_PRESETN_PWM0 0x000000B4 535c6f7c1a3SJoseph Chen #define SRST_RESETN_PWM0 0x000000B5 536c6f7c1a3SJoseph Chen #define SRST_PRESETN_PWM1 0x000000B7 537c6f7c1a3SJoseph Chen #define SRST_RESETN_PWM1 0x000000B8 538c6f7c1a3SJoseph Chen #define SRST_PRESETN_SCR 0x000000BA 539c6f7c1a3SJoseph Chen #define SRST_ARESETN_DCF 0x000000BB 540c6f7c1a3SJoseph Chen #define SRST_PRESETN_INTMUX 0x000000BC 541c6f7c1a3SJoseph Chen 542c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON25(Offset:0xA64) 543c6f7c1a3SJoseph Chen #define SRST_ARESETN_VPU_BIU 0x00000196 544c6f7c1a3SJoseph Chen #define SRST_HRESETN_VPU_BIU 0x00000197 545c6f7c1a3SJoseph Chen #define SRST_PRESETN_VPU_BIU 0x00000198 546c6f7c1a3SJoseph Chen #define SRST_ARESETN_VPU 0x00000199 547c6f7c1a3SJoseph Chen #define SRST_HRESETN_VPU 0x0000019A 548c6f7c1a3SJoseph Chen #define SRST_PRESETN_CRU_PCIE 0x0000019B 549c6f7c1a3SJoseph Chen #define SRST_PRESETN_VPU_GRF 0x0000019C 550c6f7c1a3SJoseph Chen #define SRST_HRESETN_SFC 0x0000019D 551c6f7c1a3SJoseph Chen #define SRST_SRESETN_SFC 0x0000019E 552c6f7c1a3SJoseph Chen #define SRST_CRESETN_EMMC 0x0000019F 553c6f7c1a3SJoseph Chen 554c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON26(Offset:0xA68) 555c6f7c1a3SJoseph Chen #define SRST_HRESETN_EMMC 0x000001A0 556c6f7c1a3SJoseph Chen #define SRST_ARESETN_EMMC 0x000001A1 557c6f7c1a3SJoseph Chen #define SRST_BRESETN_EMMC 0x000001A2 558c6f7c1a3SJoseph Chen #define SRST_TRESETN_EMMC 0x000001A3 559c6f7c1a3SJoseph Chen #define SRST_PRESETN_GPIO1 0x000001A4 560c6f7c1a3SJoseph Chen #define SRST_DBRESETN_GPIO1 0x000001A5 561c6f7c1a3SJoseph Chen #define SRST_ARESETN_VPU_L_BIU 0x000001A6 562c6f7c1a3SJoseph Chen #define SRST_PRESETN_VPU_IOC 0x000001A8 563c6f7c1a3SJoseph Chen #define SRST_HRESETN_SAI_I2S0 0x000001A9 564c6f7c1a3SJoseph Chen #define SRST_MRESETN_SAI_I2S0 0x000001AA 565c6f7c1a3SJoseph Chen #define SRST_HRESETN_SAI_I2S2 0x000001AB 566c6f7c1a3SJoseph Chen #define SRST_MRESETN_SAI_I2S2 0x000001AC 567c6f7c1a3SJoseph Chen #define SRST_PRESETN_ACODEC 0x000001AD 568c6f7c1a3SJoseph Chen 569c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON27(Offset:0xA6C) 570c6f7c1a3SJoseph Chen #define SRST_PRESETN_GPIO3 0x000001B0 571c6f7c1a3SJoseph Chen #define SRST_DBRESETN_GPIO3 0x000001B1 572c6f7c1a3SJoseph Chen #define SRST_PRESETN_SPI1 0x000001B4 573c6f7c1a3SJoseph Chen #define SRST_RESETN_SPI1 0x000001B5 574c6f7c1a3SJoseph Chen #define SRST_PRESETN_UART2 0x000001B7 575c6f7c1a3SJoseph Chen #define SRST_SRESETN_UART2 0x000001B8 576c6f7c1a3SJoseph Chen #define SRST_PRESETN_UART5 0x000001B9 577c6f7c1a3SJoseph Chen #define SRST_SRESETN_UART5 0x000001BA 578c6f7c1a3SJoseph Chen #define SRST_PRESETN_UART6 0x000001BB 579c6f7c1a3SJoseph Chen #define SRST_SRESETN_UART6 0x000001BC 580c6f7c1a3SJoseph Chen #define SRST_PRESETN_UART7 0x000001BD 581c6f7c1a3SJoseph Chen #define SRST_SRESETN_UART7 0x000001BE 582c6f7c1a3SJoseph Chen #define SRST_PRESETN_I2C3 0x000001BF 583c6f7c1a3SJoseph Chen 584c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON28(Offset:0xA70) 585c6f7c1a3SJoseph Chen #define SRST_RESETN_I2C3 0x000001C0 586c6f7c1a3SJoseph Chen #define SRST_PRESETN_I2C5 0x000001C1 587c6f7c1a3SJoseph Chen #define SRST_RESETN_I2C5 0x000001C2 588c6f7c1a3SJoseph Chen #define SRST_PRESETN_I2C6 0x000001C3 589c6f7c1a3SJoseph Chen #define SRST_RESETN_I2C6 0x000001C4 590c6f7c1a3SJoseph Chen #define SRST_ARESETN_MAC 0x000001C5 591c6f7c1a3SJoseph Chen 592c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON30(Offset:0xA78) 593c6f7c1a3SJoseph Chen #define SRST_PRESETN_PCIE 0x000001E1 594c6f7c1a3SJoseph Chen #define SRST_RESETN_PCIE_PIPE_PHY 0x000001E2 595c6f7c1a3SJoseph Chen #define SRST_RESETN_PCIE_POWER_UP 0x000001E3 596c6f7c1a3SJoseph Chen #define SRST_PRESETN_PCIE_PHY 0x000001E6 597c6f7c1a3SJoseph Chen #define SRST_PRESETN_PIPE_GRF 0x000001E7 598c6f7c1a3SJoseph Chen 599c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON32(Offset:0xA80) 600c6f7c1a3SJoseph Chen #define SRST_HRESETN_SDIO0 0x00000202 601c6f7c1a3SJoseph Chen #define SRST_HRESETN_SDIO1 0x00000204 602c6f7c1a3SJoseph Chen #define SRST_RESETN_TS_0 0x00000205 603c6f7c1a3SJoseph Chen #define SRST_RESETN_TS_1 0x00000206 604c6f7c1a3SJoseph Chen #define SRST_PRESETN_CAN2 0x00000207 605c6f7c1a3SJoseph Chen #define SRST_RESETN_CAN2 0x00000208 606c6f7c1a3SJoseph Chen #define SRST_PRESETN_CAN3 0x00000209 607c6f7c1a3SJoseph Chen #define SRST_RESETN_CAN3 0x0000020A 608c6f7c1a3SJoseph Chen #define SRST_PRESETN_SARADC 0x0000020B 609c6f7c1a3SJoseph Chen #define SRST_RESETN_SARADC 0x0000020C 610c6f7c1a3SJoseph Chen #define SRST_RESETN_SARADC_PHY 0x0000020D 611c6f7c1a3SJoseph Chen #define SRST_PRESETN_TSADC 0x0000020E 612c6f7c1a3SJoseph Chen #define SRST_RESETN_TSADC 0x0000020F 613c6f7c1a3SJoseph Chen 614c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON33(Offset:0xA84) 615c6f7c1a3SJoseph Chen #define SRST_ARESETN_USB3OTG 0x00000211 616c6f7c1a3SJoseph Chen 617c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON34(Offset:0xA88) 618c6f7c1a3SJoseph Chen #define SRST_ARESETN_GPU_BIU 0x00000223 619c6f7c1a3SJoseph Chen #define SRST_PRESETN_GPU_BIU 0x00000225 620c6f7c1a3SJoseph Chen #define SRST_ARESETN_GPU 0x00000228 621c6f7c1a3SJoseph Chen #define SRST_RESETN_REF_PVTPLL_GPU 0x00000229 622c6f7c1a3SJoseph Chen 623c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON36(Offset:0xA90) 624c6f7c1a3SJoseph Chen #define SRST_HRESETN_RKVENC_BIU 0x00000243 625c6f7c1a3SJoseph Chen #define SRST_ARESETN_RKVENC_BIU 0x00000244 626c6f7c1a3SJoseph Chen #define SRST_PRESETN_RKVENC_BIU 0x00000245 627c6f7c1a3SJoseph Chen #define SRST_HRESETN_RKVENC 0x00000246 628c6f7c1a3SJoseph Chen #define SRST_ARESETN_RKVENC 0x00000247 629c6f7c1a3SJoseph Chen #define SRST_RESETN_CORE_RKVENC 0x00000248 630c6f7c1a3SJoseph Chen #define SRST_HRESETN_SAI_I2S1 0x00000249 631c6f7c1a3SJoseph Chen #define SRST_MRESETN_SAI_I2S1 0x0000024A 632c6f7c1a3SJoseph Chen #define SRST_PRESETN_I2C1 0x0000024B 633c6f7c1a3SJoseph Chen #define SRST_RESETN_I2C1 0x0000024C 634c6f7c1a3SJoseph Chen #define SRST_PRESETN_I2C0 0x0000024D 635c6f7c1a3SJoseph Chen #define SRST_RESETN_I2C0 0x0000024E 636c6f7c1a3SJoseph Chen 637c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON37(Offset:0xA94) 638c6f7c1a3SJoseph Chen #define SRST_PRESETN_SPI0 0x00000252 639c6f7c1a3SJoseph Chen #define SRST_RESETN_SPI0 0x00000253 640c6f7c1a3SJoseph Chen #define SRST_PRESETN_GPIO4 0x00000258 641c6f7c1a3SJoseph Chen #define SRST_DBRESETN_GPIO4 0x00000259 642c6f7c1a3SJoseph Chen #define SRST_PRESETN_RKVENC_IOC 0x0000025A 643c6f7c1a3SJoseph Chen #define SRST_HRESETN_SPDIF 0x0000025E 644c6f7c1a3SJoseph Chen #define SRST_MRESETN_SPDIF 0x0000025F 645c6f7c1a3SJoseph Chen 646c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON38(Offset:0xA98) 647c6f7c1a3SJoseph Chen #define SRST_HRESETN_PDM 0x00000260 648c6f7c1a3SJoseph Chen #define SRST_MRESETN_PDM 0x00000261 649c6f7c1a3SJoseph Chen #define SRST_PRESETN_UART1 0x00000262 650c6f7c1a3SJoseph Chen #define SRST_SRESETN_UART1 0x00000263 651c6f7c1a3SJoseph Chen #define SRST_PRESETN_UART3 0x00000264 652c6f7c1a3SJoseph Chen #define SRST_SRESETN_UART3 0x00000265 653c6f7c1a3SJoseph Chen #define SRST_PRESETN_RKVENC_GRF 0x00000266 654c6f7c1a3SJoseph Chen #define SRST_PRESETN_CAN0 0x00000267 655c6f7c1a3SJoseph Chen #define SRST_RESETN_CAN0 0x00000268 656c6f7c1a3SJoseph Chen #define SRST_PRESETN_CAN1 0x00000269 657c6f7c1a3SJoseph Chen #define SRST_RESETN_CAN1 0x0000026A 658c6f7c1a3SJoseph Chen 659c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON39(Offset:0xA9C) 660c6f7c1a3SJoseph Chen #define SRST_ARESETN_VO_BIU 0x00000273 661c6f7c1a3SJoseph Chen #define SRST_HRESETN_VO_BIU 0x00000274 662c6f7c1a3SJoseph Chen #define SRST_PRESETN_VO_BIU 0x00000275 663c6f7c1a3SJoseph Chen #define SRST_HRESETN_RGA2E 0x00000277 664c6f7c1a3SJoseph Chen #define SRST_ARESETN_RGA2E 0x00000278 665c6f7c1a3SJoseph Chen #define SRST_RESETN_CORE_RGA2E 0x00000279 666c6f7c1a3SJoseph Chen #define SRST_HRESETN_VDPP 0x0000027A 667c6f7c1a3SJoseph Chen #define SRST_ARESETN_VDPP 0x0000027B 668c6f7c1a3SJoseph Chen #define SRST_RESETN_CORE_VDPP 0x0000027C 669c6f7c1a3SJoseph Chen #define SRST_PRESETN_VO_GRF 0x0000027D 670c6f7c1a3SJoseph Chen #define SRST_PRESETN_CRU 0x0000027F 671c6f7c1a3SJoseph Chen 672c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON40(Offset:0xAA0) 673c6f7c1a3SJoseph Chen #define SRST_ARESETN_VOP_BIU 0x00000281 674c6f7c1a3SJoseph Chen #define SRST_HRESETN_VOP 0x00000282 675c6f7c1a3SJoseph Chen #define SRST_DRESETN_VOP0 0x00000283 676c6f7c1a3SJoseph Chen #define SRST_DRESETN_VOP1 0x00000284 677c6f7c1a3SJoseph Chen #define SRST_ARESETN_VOP 0x00000285 678c6f7c1a3SJoseph Chen #define SRST_PRESETN_HDMI 0x00000286 679c6f7c1a3SJoseph Chen #define SRST_HDMI_RESETN 0x00000287 680c6f7c1a3SJoseph Chen #define SRST_PRESETN_HDMIPHY 0x0000028E 681c6f7c1a3SJoseph Chen #define SRST_HRESETN_HDCP_KEY 0x0000028F 682c6f7c1a3SJoseph Chen 683c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON41(Offset:0xAA4) 684c6f7c1a3SJoseph Chen #define SRST_ARESETN_HDCP 0x00000290 685c6f7c1a3SJoseph Chen #define SRST_HRESETN_HDCP 0x00000291 686c6f7c1a3SJoseph Chen #define SRST_PRESETN_HDCP 0x00000292 687c6f7c1a3SJoseph Chen #define SRST_HRESETN_CVBS 0x00000293 688c6f7c1a3SJoseph Chen #define SRST_DRESETN_CVBS_VOP 0x00000294 689c6f7c1a3SJoseph Chen #define SRST_DRESETN_4X_CVBS_VOP 0x00000295 690c6f7c1a3SJoseph Chen #define SRST_ARESETN_JPEG_DECODER 0x00000296 691c6f7c1a3SJoseph Chen #define SRST_HRESETN_JPEG_DECODER 0x00000297 692c6f7c1a3SJoseph Chen #define SRST_ARESETN_VO_L_BIU 0x00000299 693c6f7c1a3SJoseph Chen #define SRST_ARESETN_MAC_VO 0x0000029A 694c6f7c1a3SJoseph Chen 695c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON42(Offset:0xAA8) 696c6f7c1a3SJoseph Chen #define SRST_ARESETN_JPEG_BIU 0x000002A0 697c6f7c1a3SJoseph Chen #define SRST_HRESETN_SAI_I2S3 0x000002A1 698c6f7c1a3SJoseph Chen #define SRST_MRESETN_SAI_I2S3 0x000002A2 699c6f7c1a3SJoseph Chen #define SRST_RESETN_MACPHY 0x000002A3 700c6f7c1a3SJoseph Chen #define SRST_PRESETN_VCDCPHY 0x000002A4 701c6f7c1a3SJoseph Chen #define SRST_PRESETN_GPIO2 0x000002A5 702c6f7c1a3SJoseph Chen #define SRST_DBRESETN_GPIO2 0x000002A6 703c6f7c1a3SJoseph Chen #define SRST_PRESETN_VO_IOC 0x000002A7 704c6f7c1a3SJoseph Chen #define SRST_HRESETN_SDMMC0 0x000002A9 705c6f7c1a3SJoseph Chen #define SRST_PRESETN_OTPC_NS 0x000002AB 706c6f7c1a3SJoseph Chen #define SRST_RESETN_SBPI_OTPC_NS 0x000002AC 707c6f7c1a3SJoseph Chen #define SRST_RESETN_USER_OTPC_NS 0x000002AD 708c6f7c1a3SJoseph Chen 709c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON43(Offset:0xAAC) 710c6f7c1a3SJoseph Chen #define SRST_RESETN_HDMIHDP0 0x000002B2 711c6f7c1a3SJoseph Chen #define SRST_HRESETN_USBHOST 0x000002B3 712c6f7c1a3SJoseph Chen #define SRST_HRESETN_USBHOST_ARB 0x000002B4 713c6f7c1a3SJoseph Chen #define SRST_RESETN_HOST_UTMI 0x000002B6 714c6f7c1a3SJoseph Chen #define SRST_PRESETN_UART4 0x000002B7 715c6f7c1a3SJoseph Chen #define SRST_SRESETN_UART4 0x000002B8 716c6f7c1a3SJoseph Chen #define SRST_PRESETN_I2C4 0x000002B9 717c6f7c1a3SJoseph Chen #define SRST_RESETN_I2C4 0x000002BA 718c6f7c1a3SJoseph Chen #define SRST_PRESETN_I2C7 0x000002BB 719c6f7c1a3SJoseph Chen #define SRST_RESETN_I2C7 0x000002BC 720c6f7c1a3SJoseph Chen #define SRST_PRESETN_USBPHY 0x000002BD 721c6f7c1a3SJoseph Chen #define SRST_RESETN_USBPHY_POR 0x000002BE 722c6f7c1a3SJoseph Chen #define SRST_RESETN_USBPHY_OTG 0x000002BF 723c6f7c1a3SJoseph Chen 724c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON44(Offset:0xAB0) 725c6f7c1a3SJoseph Chen #define SRST_RESETN_USBPHY_HOST 0x000002C0 726c6f7c1a3SJoseph Chen #define SRST_PRESETN_DDRPHY_CRU 0x000002C4 727c6f7c1a3SJoseph Chen #define SRST_HRESETN_RKVDEC_BIU 0x000002C6 728c6f7c1a3SJoseph Chen #define SRST_ARESETN_RKVDEC_BIU 0x000002C7 729c6f7c1a3SJoseph Chen #define SRST_ARESETN_RKVDEC 0x000002C8 730c6f7c1a3SJoseph Chen #define SRST_HRESETN_RKVDEC 0x000002C9 731c6f7c1a3SJoseph Chen #define SRST_RESETN_HEVC_CA_RKVDEC 0x000002CB 732c6f7c1a3SJoseph Chen #define SRST_RESETN_REF_PVTPLL_RKVDEC 0x000002CC 733c6f7c1a3SJoseph Chen 734c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON45(Offset:0xAB4) 735c6f7c1a3SJoseph Chen #define SRST_PRESETN_DDR_BIU 0x000002D1 736c6f7c1a3SJoseph Chen #define SRST_PRESETN_DDRC 0x000002D2 737c6f7c1a3SJoseph Chen #define SRST_PRESETN_DDRMON 0x000002D3 738c6f7c1a3SJoseph Chen #define SRST_RESETN_TIMER_DDRMON 0x000002D4 739c6f7c1a3SJoseph Chen #define SRST_PRESETN_MSCH_BIU 0x000002D5 740c6f7c1a3SJoseph Chen #define SRST_PRESETN_DDR_GRF 0x000002D6 741c6f7c1a3SJoseph Chen #define SRST_PRESETN_DDR_HWLP 0x000002D8 742c6f7c1a3SJoseph Chen #define SRST_PRESETN_DDRPHY 0x000002D9 743c6f7c1a3SJoseph Chen #define SRST_RESETN_MSCH_BIU 0x000002DA 744c6f7c1a3SJoseph Chen #define SRST_ARESETN_DDR_UPCTL 0x000002DB 745c6f7c1a3SJoseph Chen #define SRST_RESETN_DDR_UPCTL 0x000002DC 746c6f7c1a3SJoseph Chen #define SRST_RESETN_DDRMON 0x000002DD 747c6f7c1a3SJoseph Chen #define SRST_ARESETN_DDR_SCRAMBLE 0x000002DE 748c6f7c1a3SJoseph Chen #define SRST_ARESETN_SPLIT 0x000002DF 749c6f7c1a3SJoseph Chen 750c6f7c1a3SJoseph Chen // CRU_SOFTRST_CON46(Offset:0xAB8) 751c6f7c1a3SJoseph Chen #define SRST_RESETN_DDR_PHY 0x000002E0 752c6f7c1a3SJoseph Chen 753c6f7c1a3SJoseph Chen #endif 754c6f7c1a3SJoseph Chen 755