| /rk3399_rockchip-uboot/board/ti/ks2_evm/ |
| H A D | mux-k2g.h | 18 { 115, MODE(0) }, /* SOC_UART0_RXD */
19 { 116, MODE(0) }, /* SOC_UART0_TXD */
22 { 223, MODE(0) }, /* SOC_I2C0_SCL */
23 { 224, MODE(0) }, /* SOC_I2C0_SDA */
26 { 225, MODE(0) }, /* SOC_I2C1_SCL */
27 { 226, MODE(0) }, /* SOC_I2C1_SDA */
33 { 0, MODE(0) }, /* GPMCAD0 */
34 { 1, MODE(0) }, /* GPMCAD1 */
35 { 2, MODE(0) }, /* GPMCAD2 */
36 { 3, MODE(0) }, /* GPMCAD3 */
[all …]
|
| /rk3399_rockchip-uboot/board/siemens/rut/ |
| H A D | mux.c | 23 {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */
24 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
29 {OFFSET(ddr_resetn), (MODE(0))},
30 {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
31 {OFFSET(ddr_ck), (MODE(0))},
32 {OFFSET(ddr_nck), (MODE(0))},
33 {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
34 {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
35 {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
36 {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
[all …]
|
| /rk3399_rockchip-uboot/board/siemens/draco/ |
| H A D | mux.c | 23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
29 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
30 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
35 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
37 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
43 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
44 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
45 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
46 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
[all …]
|
| /rk3399_rockchip-uboot/board/bosch/shc/ |
| H A D | mux.c | 22 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_RXD */
23 {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
24 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART0_CTS */
25 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)}, /* UART0_RTS */
30 {OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART1_RXD */
31 {OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)}, /* UART1_TXD */
32 {OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)}, /* UART1_CTS */
33 {OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)}, /* UART1_RTS */
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)}, /* UART2_TXD */
[all …]
|
| /rk3399_rockchip-uboot/board/siemens/pxm2/ |
| H A D | mux.c | 24 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
25 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
26 {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
32 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
33 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
34 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
35 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
36 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
37 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
38 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
[all …]
|
| /rk3399_rockchip-uboot/board/BuR/brppt1/ |
| H A D | mux.c | 21 {OFFSET(uart0_rtsn), (MODE(0) | PULLUDEN)},
23 {OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
25 {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
32 {OFFSET(uart1_rtsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
34 {OFFSET(uart1_ctsn), (MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE)},
36 {OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
38 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
43 {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
44 {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
[all …]
|
| /rk3399_rockchip-uboot/board/BuR/brxre1/ |
| H A D | mux.c | 21 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
23 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
25 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
27 {OFFSET(spi0_cs0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
29 {OFFSET(spi0_cs1), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},
35 {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN},
37 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
43 {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN},
45 {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
51 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)},
[all …]
|
| /rk3399_rockchip-uboot/board/ti/am335x/ |
| H A D | mux.c | 26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
[all …]
|
| /rk3399_rockchip-uboot/board/ti/ti814x/ |
| H A D | mux.c | 25 {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */
26 {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */
31 {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */
32 {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */
33 {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */
34 {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */
35 {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */
36 {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */
37 {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */
38 {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */
[all …]
|
| /rk3399_rockchip-uboot/board/ti/am43xx/ |
| H A D | mux.c | 16 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
17 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
18 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
19 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
20 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
21 {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
22 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
23 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
24 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
29 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
[all …]
|
| /rk3399_rockchip-uboot/board/compulab/cm_t43/ |
| H A D | mux.c | 13 {OFFSET(mii1_txen), MODE(2)},
14 {OFFSET(mii1_txd3), MODE(2)},
15 {OFFSET(mii1_txd2), MODE(2)},
16 {OFFSET(mii1_txd1), MODE(2)},
17 {OFFSET(mii1_txd0), MODE(2)},
18 {OFFSET(mii1_txclk), MODE(2)},
19 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN},
20 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN},
21 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN},
22 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN},
[all …]
|
| /rk3399_rockchip-uboot/board/birdland/bav335x/ |
| H A D | mux.c | 26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
[all …]
|
| /rk3399_rockchip-uboot/board/vscom/baltos/ |
| H A D | mux.c | 25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
31 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
32 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
33 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
34 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
35 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
36 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
42 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
44 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
[all …]
|
| /rk3399_rockchip-uboot/board/silica/pengwyn/ |
| H A D | mux.c | 18 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
19 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
27 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
29 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
36 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
37 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
38 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
39 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
40 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
41 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
[all …]
|
| /rk3399_rockchip-uboot/board/compulab/cm_t335/ |
| H A D | mux.c | 18 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
19 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
24 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
25 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
26 {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
27 {OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
32 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
33 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
34 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
35 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
[all …]
|
| /rk3399_rockchip-uboot/board/tcl/sl50/ |
| H A D | mux.c | 18 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
19 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
24 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
25 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
30 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
31 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
36 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
37 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
42 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
43 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
[all …]
|
| /rk3399_rockchip-uboot/board/phytec/pcm051/ |
| H A D | mux.c | 25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
32 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
33 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
34 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
35 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
36 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
37 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
38 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
45 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
[all …]
|
| /rk3399_rockchip-uboot/board/isee/igep003x/ |
| H A D | mux.c | 23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
24 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
29 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
30 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
31 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
32 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
33 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
34 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
35 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
40 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
[all …]
|
| /rk3399_rockchip-uboot/board/gumstix/pepper/ |
| H A D | mux.c | 17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
18 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
23 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
24 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
25 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
26 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
27 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
28 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
29 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
35 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
[all …]
|
| /rk3399_rockchip-uboot/board/grinn/chiliboard/ |
| H A D | board.c | 34 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
35 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
40 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
41 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
42 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
43 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
44 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
45 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
50 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
51 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
[all …]
|
| /rk3399_rockchip-uboot/arch/arm/mach-omap2/am33xx/ |
| H A D | chilisom.c | 30 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
32 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
38 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
39 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
40 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
41 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
42 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
43 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
44 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
45 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
[all …]
|
| /rk3399_rockchip-uboot/board/ti/ti816x/ |
| H A D | evm.c | 64 { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
65 { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
66 { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
67 { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
68 { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
69 { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
70 { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
|
| /rk3399_rockchip-uboot/drivers/power/regulator/ |
| H A D | max77686.c | 21 #define MODE(_id, _val, _name) { \ macro
29 MODE(OPMODE_OFF, MAX77686_LDO_MODE_OFF, "OFF"),
30 MODE(OPMODE_LPM, MAX77686_LDO_MODE_LPM, "LPM"),
31 MODE(OPMODE_STANDBY_LPM, MAX77686_LDO_MODE_STANDBY_LPM, "ON/LPM"),
32 MODE(OPMODE_ON, MAX77686_LDO_MODE_ON, "ON"),
37 MODE(OPMODE_OFF, MAX77686_LDO_MODE_OFF, "OFF"),
38 MODE(OPMODE_STANDBY, MAX77686_LDO_MODE_STANDBY, "ON/OFF"),
39 MODE(OPMODE_STANDBY_LPM, MAX77686_LDO_MODE_STANDBY_LPM, "ON/LPM"),
40 MODE(OPMODE_ON, MAX77686_LDO_MODE_ON, "ON"),
45 MODE(OPMODE_OFF, MAX77686_BUCK_MODE_OFF, "OFF"),
[all …]
|
| H A D | pfuze100.c | 213 #define MODE(_id, _val, _name) { \ macro
221 MODE(OFF_OFF, OFF_OFF, "OFF_OFF"),
222 MODE(PWM_OFF, PWM_OFF, "PWM_OFF"),
223 MODE(PFM_OFF, PFM_OFF, "PFM_OFF"),
224 MODE(APS_OFF, APS_OFF, "APS_OFF"),
225 MODE(PWM_PWM, PWM_PWM, "PWM_PWM"),
226 MODE(PWM_APS, PWM_APS, "PWM_APS"),
227 MODE(APS_APS, APS_APS, "APS_APS"),
228 MODE(APS_PFM, APS_PFM, "APS_PFM"),
229 MODE(PWM_PFM, PWM_PFM, "PWM_PFM"),
[all …]
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3528/ |
| H A D | rk3528.c | 236 #define set_uart_iomux_rx(ID, MODE) \ argument
237 …set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR…
238 #define set_uart_iomux_tx(ID, MODE) \ argument
239 …set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR…
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