1 /*
2 * Copyright (c) 2020 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <dm.h>
8 #include <misc.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/grf_rk3528.h>
13 #include <asm/arch/ioc_rk3528.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 #define FIREWALL_DDR_BASE 0xff2e0000
18 #define FW_DDR_MST1_REG 0x44
19 #define FW_DDR_MST6_REG 0x58
20 #define FW_DDR_MST7_REG 0x5c
21 #define FW_DDR_MST11_REG 0x6c
22 #define FW_DDR_MST14_REG 0x78
23 #define FW_DDR_MST16_REG 0x80
24 #define FW_DDR_MST_REG 0xf0
25
26 #define VENC_GRF_BASE 0xff320000
27 #define VENC_GRF_CON1 0x4
28
29 #define VPU_GRF_BASE 0xff340000
30 #define VPU_GRF_CON4 0x14
31
32 #define PMU_SGRF_BASE 0xff440000
33 #define PMU_SGRF_SOC_CON4 0x10
34 #define PMU_SGRF_SOC_CON5 0x14
35 #define PMU_SGRF_SOC_CON6 0x18
36 #define PMU_SGRF_SOC_CON8 0x20
37 #define PMU_SGRF_SOC_CON11 0x2c
38
39 #define PMU_CRU_BASE 0xff4b0000
40 #define PMU_CRU_GATE_CON00 0x800
41 #define PMU_CRU_SOFTRST_CON00 0xa00
42
43 #define GPIO1C_IOMUX_SEL_H 0x034
44 #define GPIO1D_IOMUX_SEL_L 0x038
45 #define GPIO1D_IOMUX_SEL_H 0x03c
46
47 #define CPU_PRIORITY_REG 0xff210008
48 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
49
50 #ifdef CONFIG_ARM64
51 #include <asm/armv8/mmu.h>
52
53 static struct mm_region rk3528_mem_map[] = {
54 {
55 .virt = 0x0UL,
56 .phys = 0x0UL,
57 .size = 0xfc000000UL,
58 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
59 PTE_BLOCK_INNER_SHARE
60 }, {
61 .virt = 0xfc000000UL,
62 .phys = 0xfc000000UL,
63 .size = 0x04000000UL,
64 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
65 PTE_BLOCK_NON_SHARE |
66 PTE_BLOCK_PXN | PTE_BLOCK_UXN
67 }, {
68 /* List terminator */
69 0,
70 }
71 };
72
73 struct mm_region *mem_map = rk3528_mem_map;
74 #endif
75
76 #define GPIO0_IOC_BASE 0xFF540000
77 #define GPIO1_IOC_BASE 0xFF560000
78 #define GPIO2_IOC_BASE 0xFF570000
79 #define GPIO3_IOC_BASE 0xFF560000
80 #define GPIO4_IOC_BASE 0xFF550000
81
82 #define GPIO1_IOC_GPIO1D_IOMUX_SEL_L (GPIO1_IOC_BASE + 0x38)
83 #define GPIO1_IOC_GPIO1C_DS_2 (GPIO1_IOC_BASE + 0x148)
84 #define GPIO1_IOC_GPIO1C_DS_3 (GPIO1_IOC_BASE + 0x14C)
85 #define GPIO1_IOC_GPIO1D_DS_0 (GPIO1_IOC_BASE + 0x150)
86 #define GPIO1_IOC_GPIO1D_DS_1 (GPIO1_IOC_BASE + 0x154)
87 #define GPIO1_IOC_GPIO1D_DS_2 (GPIO1_IOC_BASE + 0x158)
88
89 /* uart0 iomux */
90 /* gpio4c7 */
91 #define UART0_RX_M0 1
92 #define UART0_RX_M0_OFFSET 12
93 #define UART0_RX_M0_ADDR (GPIO4_IOC_BASE + 0x94)
94 /* gpio4d0 */
95 #define UART0_TX_M0 1
96 #define UART0_TX_M0_OFFSET 0
97 #define UART0_TX_M0_ADDR (GPIO4_IOC_BASE + 0x98)
98
99 /* gpio2a0 */
100 #define UART0_RX_M1 2
101 #define UART0_RX_M1_OFFSET 0
102 #define UART0_RX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
103 /* gpio2a1 */
104 #define UART0_TX_M1 2
105 #define UART0_TX_M1_OFFSET 4
106 #define UART0_TX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
107
108 /* uart1 iomux */
109 /* gpio4a7 */
110 #define UART1_RX_M0 2
111 #define UART1_RX_M0_OFFSET 12
112 #define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
113 /* gpio4a6 */
114 #define UART1_TX_M0 2
115 #define UART1_TX_M0_OFFSET 8
116 #define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
117
118 /* gpio4c6 */
119 #define UART1_RX_M1 2
120 #define UART1_RX_M1_OFFSET 8
121 #define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
122 /* gpio4c5 */
123 #define UART1_TX_M1 2
124 #define UART1_TX_M1_OFFSET 4
125 #define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
126
127 /* uart2 iomux */
128 /* gpio3a0 */
129 #define UART2_RX_M0 1
130 #define UART2_RX_M0_OFFSET 0
131 #define UART2_RX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
132 /* gpio3a1 */
133 #define UART2_TX_M0 1
134 #define UART2_TX_M0_OFFSET 4
135 #define UART2_TX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
136
137 /* gpio1b0 */
138 #define UART2_RX_M1 1
139 #define UART2_RX_M1_OFFSET 0
140 #define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
141 /* gpio1b1 */
142 #define UART2_TX_M1 1
143 #define UART2_TX_M1_OFFSET 4
144 #define UART2_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
145
146 /* uart3 iomux */
147 /* gpio4b0 */
148 #define UART3_RX_M0 2
149 #define UART3_RX_M0_OFFSET 0
150 #define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
151 /* gpio4b1 */
152 #define UART3_TX_M0 2
153 #define UART3_TX_M0_OFFSET 4
154 #define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
155
156 /* gpio4b7 */
157 #define UART3_RX_M1 3
158 #define UART3_RX_M1_OFFSET 12
159 #define UART3_RX_M1_ADDR (GPIO4_IOC_BASE + 0x8C)
160 /* gpio4c0 */
161 #define UART3_TX_M1 3
162 #define UART3_TX_M1_OFFSET 0
163 #define UART3_TX_M1_ADDR (GPIO4_IOC_BASE + 0x90)
164
165 /* uart4 iomux */
166 /* gpio2a2 */
167 #define UART4_RX_M0 3
168 #define UART4_RX_M0_OFFSET 8
169 #define UART4_RX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
170 /* gpio2a3 */
171 #define UART4_TX_M0 3
172 #define UART4_TX_M0_OFFSET 12
173 #define UART4_TX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
174
175 /* uart5 iomux */
176 /* gpio1a2 */
177 #define UART5_RX_M0 2
178 #define UART5_RX_M0_OFFSET 8
179 #define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
180 /* gpio1a3 */
181 #define UART5_TX_M0 2
182 #define UART5_TX_M0_OFFSET 12
183 #define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
184
185 /* gpio1d4 */
186 #define UART5_RX_M1 2
187 #define UART5_RX_M1_OFFSET 0
188 #define UART5_RX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
189 /* gpio1d7 */
190 #define UART5_TX_M1 2
191 #define UART5_TX_M1_OFFSET 12
192 #define UART5_TX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
193
194 /* uart6 iomux */
195 /* gpio3a7 */
196 #define UART6_RX_M0 4
197 #define UART6_RX_M0_OFFSET 12
198 #define UART6_RX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
199 /* gpio3a6 */
200 #define UART6_TX_M0 4
201 #define UART6_TX_M0_OFFSET 8
202 #define UART6_TX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
203
204 /* gpio3c3 */
205 #define UART6_RX_M1 4
206 #define UART6_RX_M1_OFFSET 12
207 #define UART6_RX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
208 /* gpio3c1 */
209 #define UART6_TX_M1 4
210 #define UART6_TX_M1_OFFSET 4
211 #define UART6_TX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
212
213 /* uart7 iomux */
214 /* gpio3b3 */
215 #define UART7_RX_M0 4
216 #define UART7_RX_M0_OFFSET 12
217 #define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
218 /* gpio3b2 */
219 #define UART7_TX_M0 4
220 #define UART7_TX_M0_OFFSET 8
221 #define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
222
223 /* gpio1b3 */
224 #define UART7_RX_M1 4
225 #define UART7_RX_M1_OFFSET 12
226 #define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
227 /* gpio1b2 */
228 #define UART7_TX_M1 4
229 #define UART7_TX_M1_OFFSET 8
230 #define UART7_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
231
232
233 #define set_uart_iomux(bits_offset, bits_val, addr) \
234 writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
235
236 #define set_uart_iomux_rx(ID, MODE) \
237 set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
238 #define set_uart_iomux_tx(ID, MODE) \
239 set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
240
board_debug_uart_init(void)241 void board_debug_uart_init(void)
242 {
243 /* UART 0 */
244 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f0000)
245 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
246 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
247
248 /* UART0_M0 Switch iomux */
249 set_uart_iomux_rx(0, 0);
250 set_uart_iomux_tx(0, 0);
251 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
252 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
253
254 /* UART0_M1 Switch iomux */
255 set_uart_iomux_rx(0, 1);
256 set_uart_iomux_tx(0, 1);
257 #endif
258 /* UART 1 */
259 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f8000)
260 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
261 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
262
263 /* UART1_M0 Switch iomux */
264 set_uart_iomux_rx(1, 0);
265 set_uart_iomux_tx(1, 0);
266 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
267 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
268
269 /* UART1_M1 Switch iomux */
270 set_uart_iomux_rx(1, 1);
271 set_uart_iomux_tx(1, 1);
272 #endif
273 /* UART 2 */
274 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa00000)
275 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
276 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
277
278 /* UART2_M0 Switch iomux */
279 set_uart_iomux_rx(2, 0);
280 set_uart_iomux_tx(2, 0);
281 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
282 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
283
284 /* UART2_M1 Switch iomux */
285 set_uart_iomux_rx(2, 1);
286 set_uart_iomux_tx(2, 1);
287 #endif
288 /* UART 3 */
289 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa08000)
290 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
291 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
292
293 /* UART3_M0 Switch iomux */
294 set_uart_iomux_rx(3, 0);
295 set_uart_iomux_tx(3, 0);
296 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
297 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
298
299 /* UART3_M1 Switch iomux */
300 set_uart_iomux_rx(3, 1);
301 set_uart_iomux_tx(3, 1);
302 #endif
303 /* UART 4 */
304 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa10000)
305 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
306 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
307
308 /* UART4_M0 Switch iomux */
309 set_uart_iomux_rx(4, 0);
310 set_uart_iomux_tx(4, 0);
311 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
312 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
313
314 /* UART4_M1 Switch iomux */
315 set_uart_iomux_rx(4, 1);
316 set_uart_iomux_tx(4, 1);
317 #endif
318 /* UART 5 */
319 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa18000)
320 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
321 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
322
323 /* UART5_M0 Switch iomux */
324 set_uart_iomux_rx(5, 0);
325 set_uart_iomux_tx(5, 0);
326 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
327 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
328
329 /* UART5_M1 Switch iomux */
330 set_uart_iomux_rx(5, 1);
331 set_uart_iomux_tx(5, 1);
332 #endif
333 /* UART 6 */
334 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa20000)
335 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
336 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
337
338 /* UART6_M0 Switch iomux */
339 set_uart_iomux_rx(6, 0);
340 set_uart_iomux_tx(6, 0);
341 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
342 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
343
344 /* UART6_M1 Switch iomux */
345 set_uart_iomux_rx(6, 1);
346 set_uart_iomux_tx(6, 1);
347 #endif
348 /* UART 7 */
349 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa28000)
350 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
351 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
352
353 /* UART7_M0 Switch iomux */
354 set_uart_iomux_rx(7, 0);
355 set_uart_iomux_tx(7, 0);
356 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
357 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
358
359 /* UART7_M1 Switch iomux */
360 set_uart_iomux_rx(7, 1);
361 set_uart_iomux_tx(7, 1);
362 #endif
363 #endif
364 }
365
366 #ifdef CONFIG_SPL_BUILD
rockchip_stimer_init(void)367 void rockchip_stimer_init(void)
368 {
369 /* If Timer already enabled, don't re-init it */
370 u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
371
372 if (reg & 0x1)
373 return;
374
375 asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
376 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
377 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
378 dsb();
379 writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
380 }
381 #endif
382
arch_cpu_init(void)383 int arch_cpu_init(void)
384 {
385 #if defined(CONFIG_SPL_BUILD)
386 u32 val;
387
388 /*
389 * Select clk_tx source as default for i2s2/i2s3
390 * Set I2Sx_MCLK as input default
391 *
392 * It's safe to set mclk as input default to avoid high freq glitch
393 * which may make devices work unexpected. And then enabled by
394 * kernel stage or any state where user use it.
395 */
396 writel(0x00020002, VPU_GRF_BASE + VPU_GRF_CON4);
397 writel(0x40004000, VENC_GRF_BASE + VENC_GRF_CON1);
398
399 /* Set the emmc to access ddr memory */
400 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
401 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
402
403 /* Set the sdmmc to access ddr memory */
404 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
405 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
406
407 /* Set the crypto to access ddr memory */
408 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
409 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
410
411 #if defined(CONFIG_ROCKCHIP_SFC)
412 /* Set the fspi to access ddr memory */
413 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
414 writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
415 #endif
416
417 #ifndef CONFIG_TPL_BUILD
418 /* Set cpu qos priority, then
419 * Peri > VOP > CPU = RKVDEC/RKVENC/VPU > GPU/RGA/Other
420 */
421 writel(QOS_PRIORITY_LEVEL(2, 2), CPU_PRIORITY_REG);
422 #endif
423
424 if (readl(GPIO1_IOC_GPIO1D_IOMUX_SEL_L) == 0x1111) {
425 /*
426 * set the emmc io drive strength:
427 * data and cmd: level 3
428 * clock: level 5
429 */
430 writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_2);
431 writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_3);
432 writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_0);
433 writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_1);
434 writel(0x3F3F3F0F, GPIO1_IOC_GPIO1D_DS_2);
435 }
436
437 #elif defined(CONFIG_SUPPORT_USBPLUG)
438 u32 val;
439
440 /* Set the usb to access ddr memory */
441 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
442 writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
443
444 /* Set the emmc to access ddr memory */
445 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
446 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
447
448 /* Set emmc iomux */
449 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
450 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
451 writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
452
453 #if defined(CONFIG_ROCKCHIP_SFC)
454 /* Set the fspi to access ddr memory */
455 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
456 writel(val & 0xFFFF0000uL, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
457
458 /* Set fspi iomux */
459 writel(0xffff2222, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
460 writel(0x000f0002, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
461 writel(0x00f00020, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
462 #endif
463
464 #endif
465 return 0;
466 }
467
468 #ifdef CONFIG_SPL_BUILD
spl_fit_standalone_release(char * id,uintptr_t entry_point)469 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
470 {
471 u32 val;
472
473 /* open clk_pmu_mcu_jtag / clk_mcu_32k_en / fclk_mcu_en */
474 writel(0x05800000, PMU_CRU_BASE + PMU_CRU_GATE_CON00);
475 /* set the mcu to access ddr memory */
476 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
477 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
478 /* writel(0x00000000, FIREWALL_DDR_BASE + FW_DDR_MST_REG); */
479 /* set the mcu to secure */
480 writel(0x00200000, PMU_SGRF_BASE + PMU_SGRF_SOC_CON4);
481 /* open mcu_debug_en / mcu_dclk_en / mcu_hclk_en / mcu_sclk_en */
482 writel(0x000f000f, PMU_SGRF_BASE + PMU_SGRF_SOC_CON5);
483 /* set start addr, mcu_code_addr_start */
484 writel(0xffff0000 | (entry_point >> 16), PMU_SGRF_BASE + PMU_SGRF_SOC_CON6);
485 /* mcu_tcm_addr_start, multiplex pmu sram address */
486 writel(0xffffff10, PMU_SGRF_BASE + PMU_SGRF_SOC_CON11);
487 /* jtag_mcu_m0 gpio2a4/gpio2a5 iomux */
488 /* writel(0x00ff0022, GPIO2_IOC_BASE + 0x44); */
489 /* release the mcu */
490 writel(0x00800000, PMU_CRU_BASE + PMU_CRU_SOFTRST_CON00);
491
492 return 0;
493 }
494 #endif
495
496 #define CHIP_TYPE_OFF 40
497
fdt_fixup_modules(void * blob)498 static int fdt_fixup_modules(void *blob)
499 {
500 struct udevice *dev;
501 char *compat;
502 u8 chip_type;
503 int ret;
504
505 ret = uclass_get_device_by_driver(UCLASS_MISC,
506 DM_GET_DRIVER(rockchip_otp), &dev);
507 if (ret) {
508 printf("can't get otp device, ret=%d\n", ret);
509 return ret;
510 }
511
512 ret = misc_read(dev, CHIP_TYPE_OFF, &chip_type, 1);
513 if (ret) {
514 printf("can't read chip type, ret=%d\n", ret);
515 return ret;
516 }
517
518 compat = (char *)fdt_getprop(blob, 0, "compatible", NULL);
519 fdt_setprop_string(blob, 0, "compatible", compat);
520
521 if (chip_type == 0x1)
522 fdt_appendprop_string(blob, 0, "compatible", "rockchip,rk3528");
523 else
524 fdt_appendprop_string(blob, 0, "compatible", "rockchip,rk3528a");
525
526 return 0;
527 }
528
rk_board_dm_fdt_fixup(const void * blob)529 int rk_board_dm_fdt_fixup(const void *blob)
530 {
531 return fdt_fixup_modules((void *)blob);
532 }
533