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Searched refs:MHz (Results 1 – 25 of 185) sorted by relevance

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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h78 #define MHz 1000000 macro
80 #define OSC_HZ (24*MHz)
81 #define APLL_HZ (600*MHz)
82 #define GPLL_HZ (800 * MHz)
83 #define CPLL_HZ (384*MHz)
84 #define NPLL_HZ (600 * MHz)
85 #define PPLL_HZ (676*MHz)
87 #define PMU_PCLK_HZ (48*MHz)
89 #define ACLKM_CORE_HZ (300*MHz)
90 #define ATCLK_CORE_HZ (300*MHz)
[all …]
H A Dcru_rv1126.h12 #define MHz 1000000 macro
14 #define OSC_HZ (24 * MHz)
17 #define APLL_HZ (1008 * MHz)
19 #define APLL_HZ (816 * MHz)
21 #define GPLL_HZ (1188 * MHz)
22 #define CPLL_HZ (500 * MHz)
23 #define HPLL_HZ (1400 * MHz)
24 #define PCLK_PDPMU_HZ (100 * MHz)
26 #define ACLK_PDBUS_HZ (396 * MHz)
28 #define ACLK_PDBUS_HZ (500 * MHz)
[all …]
H A Dcru_rk322x.h11 #define MHz 1000 * 1000 macro
12 #define OSC_HZ (24 * MHz)
13 #define APLL_HZ (600 * MHz)
14 #define GPLL_HZ (1200 * MHz)
15 #define CPLL_HZ (500 * MHz)
16 #define ACLK_BUS_HZ (150 * MHz)
17 #define ACLK_PERI_HZ (150 * MHz)
H A Dcru_px30.h11 #define MHz 1000000 macro
13 #define OSC_HZ (24 * MHz)
15 #define APLL_HZ (600 * MHz)
16 #define GPLL_HZ (1200 * MHz)
17 #define NPLL_HZ (1188 * MHz)
18 #define ACLK_BUS_HZ (200 * MHz)
19 #define HCLK_BUS_HZ (150 * MHz)
20 #define PCLK_BUS_HZ (100 * MHz)
21 #define ACLK_PERI_HZ (200 * MHz)
22 #define HCLK_PERI_HZ (150 * MHz)
[all …]
H A Dcru_rk3328.h72 #define MHz 1000 * 1000 macro
73 #define OSC_HZ (24 * MHz)
74 #define APLL_HZ (600 * MHz)
76 #define CPLL_HZ (1200 * MHz)
77 #define ACLK_BUS_HZ (150 * MHz)
78 #define ACLK_PERI_HZ (150 * MHz)
79 #define PWM_CLOCK_HZ (74 * MHz)
H A Dcru_rk3128.h12 #define MHz 1000000 macro
13 #define OSC_HZ (24 * MHz)
15 #define APLL_HZ (600 * MHz)
16 #define GPLL_HZ (594 * MHz)
17 #define CPLL_HZ (400 * MHz)
H A Dcru_rv1106.h12 #define MHz 1000000 macro
14 #define OSC_HZ (24 * MHz)
17 #define APLL_HZ (1104 * MHz)
19 #define APLL_HZ (816 * MHz)
21 #define GPLL_HZ (1188 * MHz)
22 #define CPLL_HZ (1000 * MHz)
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rv1106.c86 rate = 400 * MHz; in rv1106_peri_get_clk()
88 rate = 200 * MHz; in rv1106_peri_get_clk()
90 rate = 100 * MHz; in rv1106_peri_get_clk()
98 rate = 200 * MHz; in rv1106_peri_get_clk()
100 rate = 100 * MHz; in rv1106_peri_get_clk()
102 rate = 50 * MHz; in rv1106_peri_get_clk()
110 rate = 100 * MHz; in rv1106_peri_get_clk()
112 rate = 50 * MHz; in rv1106_peri_get_clk()
120 rate = 300 * MHz; in rv1106_peri_get_clk()
122 rate = 200 * MHz; in rv1106_peri_get_clk()
[all …]
H A Dclk_rk3568.c746 rate = 200 * MHz; in rk3568_bus_get_clk()
748 rate = 150 * MHz; in rk3568_bus_get_clk()
750 rate = 100 * MHz; in rk3568_bus_get_clk()
759 rate = 100 * MHz; in rk3568_bus_get_clk()
761 rate = 75 * MHz; in rk3568_bus_get_clk()
763 rate = 50 * MHz; in rk3568_bus_get_clk()
782 if (rate == 200 * MHz) in rk3568_bus_set_clk()
784 else if (rate == 150 * MHz) in rk3568_bus_set_clk()
786 else if (rate == 100 * MHz) in rk3568_bus_set_clk()
796 if (rate == 100 * MHz) in rk3568_bus_set_clk()
[all …]
H A Dclk_rk3588.c162 rate = 702 * MHz; in rk3588_center_get_clk()
164 rate = 396 * MHz; in rk3588_center_get_clk()
166 rate = 200 * MHz; in rk3588_center_get_clk()
175 rate = 500 * MHz; in rk3588_center_get_clk()
177 rate = 250 * MHz; in rk3588_center_get_clk()
179 rate = 100 * MHz; in rk3588_center_get_clk()
188 rate = 396 * MHz; in rk3588_center_get_clk()
190 rate = 200 * MHz; in rk3588_center_get_clk()
192 rate = 100 * MHz; in rk3588_center_get_clk()
201 rate = 200 * MHz; in rk3588_center_get_clk()
[all …]
H A Dclk_rv1103b.c72 rate = 600 * MHz; in rv1103b_peri_get_clk()
74 rate = 480 * MHz; in rv1103b_peri_get_clk()
76 rate = 400 * MHz; in rv1103b_peri_get_clk()
82 rate = 300 * MHz; in rv1103b_peri_get_clk()
84 rate = 200 * MHz; in rv1103b_peri_get_clk()
121 if (rate >= 594 * MHz) in rv1103b_peri_set_clk()
123 else if (rate >= 480 * MHz) in rv1103b_peri_set_clk()
132 if (rate >= 297 * MHz) in rv1103b_peri_set_clk()
196 rate = 100 * MHz; in rv1103b_i2c_get_clk()
228 rate = 300 * MHz; in rv1103b_crypto_get_clk()
[all …]
/rk3399_rockchip-uboot/doc/
H A DREADME.Heterogeneous-SoCs90 CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
91 DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
92 DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
93 CCB:666.667 MHz,
94 DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
95 CPRI:600 MHz
96 MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
97 FMAN1: 666.667 MHz
98 QMAN: 333.333 MHz
H A DREADME.fsl-hwconfig11 route either a 11.2896MHz or a 12.288MHz clock. The default is
12 12.288MHz. This option has two effects. First, the MUX on the board
18 Select the 11.2896MHz clock
21 Select the 12.288MHz clock
/rk3399_rockchip-uboot/board/freescale/t102xqds/
H A Dt1024_spi_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_sd_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_nand_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A DREADME114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
115 - Software programmable in 1 MHz increments from 1-200 MHz.
118 - 100 MHz, 125 MHz and 156.25 MHz options.
119 - Spread-spectrum option for 100 MHz.
196 0x6F 100MHz 125MHz 1101
197 0xD6 100MHz 100MHz 1111
198 0x99 156.25MHz 100MHz 1011
204 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
205 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
206 Bin3: 1000MHz 1600MT/s 400MHz 500MHz
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A DREADME23 ECC), up to 1333 MHz data rate
73 Core MHz/CCB MHz/DDR(MT/s)
74 1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
75 (SYSCLK = 100MHz, DDRCLK = 100MHz)
76 2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
77 (SYSCLK = 100MHz, DDRCLK = 133MHz)
/rk3399_rockchip-uboot/board/freescale/t208xrdb/
H A Dt2080_sd_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
H A Dt2080_nand_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
H A Dt2080_spi_rcw.cfg5 #SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
15 #SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
/rk3399_rockchip-uboot/board/boundary/nitrogen6x/
H A Dddr-setup.cfg19 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
21 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
23 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
/rk3399_rockchip-uboot/board/freescale/p1022ds/
H A DREADME13 'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
17 is 11MHz), disable eTsec2 and TDM
20 and AUDIO codec clock sources only setting as 11MHz or 12MHz !
/rk3399_rockchip-uboot/board/toradex/colibri_imx6/
H A Dddr-setup.cfg20 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
22 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
24 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
/rk3399_rockchip-uboot/board/toradex/apalis_imx6/
H A Dddr-setup.cfg20 * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
22 * MX6DL ddr is limited to 800 MHz(400 MHz clock)
24 * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)

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