1*a02d517bSMax Krummenacher/* 2*a02d517bSMax Krummenacher * Copyright (C) 2013 Boundary Devices 3*a02d517bSMax Krummenacher * Copyright (C) 2014-2016, Toradex AG 4*a02d517bSMax Krummenacher * 5*a02d517bSMax Krummenacher * SPDX-License-Identifier: GPL-2.0+ 6*a02d517bSMax Krummenacher * 7*a02d517bSMax Krummenacher * Device Configuration Data (DCD) 8*a02d517bSMax Krummenacher * 9*a02d517bSMax Krummenacher * Each entry must have the format: 10*a02d517bSMax Krummenacher * Addr-type Address Value 11*a02d517bSMax Krummenacher * 12*a02d517bSMax Krummenacher * where: 13*a02d517bSMax Krummenacher * Addr-type register length (1,2 or 4 bytes) 14*a02d517bSMax Krummenacher * Address absolute address of the register 15*a02d517bSMax Krummenacher * value value to be stored in the register 16*a02d517bSMax Krummenacher */ 17*a02d517bSMax Krummenacher 18*a02d517bSMax Krummenacher/* 19*a02d517bSMax Krummenacher * DDR3 settings 20*a02d517bSMax Krummenacher * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), 21*a02d517bSMax Krummenacher * memory bus width: 64 bits x16/x32/x64 22*a02d517bSMax Krummenacher * MX6DL ddr is limited to 800 MHz(400 MHz clock) 23*a02d517bSMax Krummenacher * memory bus width: 64 bits x16/x32/x64 24*a02d517bSMax Krummenacher * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) 25*a02d517bSMax Krummenacher * memory bus width: 32 bits x16/x32 26*a02d517bSMax Krummenacher */ 27*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 28*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 29*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 30*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 31*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 32*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 33*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 34*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 35*a02d517bSMax Krummenacher 36*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_B0DS, 0x00000030 37*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_B1DS, 0x00000030 38*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_B2DS, 0x00000030 39*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_B3DS, 0x00000030 40*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_B4DS, 0x00000030 41*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_B5DS, 0x00000030 42*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_B6DS, 0x00000030 43*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_B7DS, 0x00000030 44*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 45*a02d517bSMax Krummenacher/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 46*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 47*a02d517bSMax Krummenacher 48*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 49*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 50*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 51*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 52*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 53*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 54*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 55*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 56*a02d517bSMax Krummenacher 57*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_CAS, 0x00020030 58*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_RAS, 0x00020030 59*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 60*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 61*a02d517bSMax Krummenacher 62*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_RESET, 0x00020030 63*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 64*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 65*a02d517bSMax Krummenacher 66*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 67*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 68*a02d517bSMax Krummenacher 69*a02d517bSMax Krummenacher/* (differential input) */ 70*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 71*a02d517bSMax Krummenacher/* (differential input) */ 72*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 73*a02d517bSMax Krummenacher/* disable ddr pullups */ 74*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 75*a02d517bSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 76*a02d517bSMax Krummenacher/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 77*a02d517bSMax KrummenacherDATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 78*a02d517bSMax Krummenacher 79*a02d517bSMax Krummenacher/* Read data DQ Byte0-3 delay */ 80*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 81*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 82*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 83*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 84*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 85*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 86*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 87*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 88*a02d517bSMax Krummenacher 89*a02d517bSMax Krummenacher/* 90*a02d517bSMax Krummenacher * MDMISC mirroring interleaved (row/bank/col) 91*a02d517bSMax Krummenacher */ 92*a02d517bSMax Krummenacher/* TODO: check what the RALAT field does */ 93*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 94*a02d517bSMax Krummenacher 95*a02d517bSMax Krummenacher/* 96*a02d517bSMax Krummenacher * MDSCR con_req 97*a02d517bSMax Krummenacher */ 98*a02d517bSMax KrummenacherDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 99