1*592f4aedSMax Krummenacher/* 2*592f4aedSMax Krummenacher * Copyright (C) 2013 Boundary Devices 3*592f4aedSMax Krummenacher * Copyright (C) 2014-2016, Toradex AG 4*592f4aedSMax Krummenacher * 5*592f4aedSMax Krummenacher * SPDX-License-Identifier: GPL-2.0+ 6*592f4aedSMax Krummenacher * 7*592f4aedSMax Krummenacher * Device Configuration Data (DCD) 8*592f4aedSMax Krummenacher * 9*592f4aedSMax Krummenacher * Each entry must have the format: 10*592f4aedSMax Krummenacher * Addr-type Address Value 11*592f4aedSMax Krummenacher * 12*592f4aedSMax Krummenacher * where: 13*592f4aedSMax Krummenacher * Addr-type register length (1,2 or 4 bytes) 14*592f4aedSMax Krummenacher * Address absolute address of the register 15*592f4aedSMax Krummenacher * value value to be stored in the register 16*592f4aedSMax Krummenacher */ 17*592f4aedSMax Krummenacher 18*592f4aedSMax Krummenacher/* 19*592f4aedSMax Krummenacher * DDR3 settings 20*592f4aedSMax Krummenacher * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock), 21*592f4aedSMax Krummenacher * memory bus width: 64 bits x16/x32/x64 22*592f4aedSMax Krummenacher * MX6DL ddr is limited to 800 MHz(400 MHz clock) 23*592f4aedSMax Krummenacher * memory bus width: 64 bits x16/x32/x64 24*592f4aedSMax Krummenacher * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) 25*592f4aedSMax Krummenacher * memory bus width: 32 bits x16/x32 26*592f4aedSMax Krummenacher */ 27*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 28*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 29*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 30*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 31*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 32*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 33*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 34*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 35*592f4aedSMax Krummenacher 36*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_B0DS, 0x00000030 37*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_B1DS, 0x00000030 38*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_B2DS, 0x00000030 39*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_B3DS, 0x00000030 40*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_B4DS, 0x00000030 41*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_B5DS, 0x00000030 42*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_B6DS, 0x00000030 43*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_B7DS, 0x00000030 44*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 45*592f4aedSMax Krummenacher/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 46*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 47*592f4aedSMax Krummenacher 48*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 49*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 50*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 51*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 52*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 53*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 54*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 55*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 56*592f4aedSMax Krummenacher 57*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_CAS, 0x00020030 58*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_RAS, 0x00020030 59*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 60*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 61*592f4aedSMax Krummenacher 62*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_RESET, 0x00020030 63*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 64*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 65*592f4aedSMax Krummenacher 66*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 67*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 68*592f4aedSMax Krummenacher 69*592f4aedSMax Krummenacher/* (differential input) */ 70*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 71*592f4aedSMax Krummenacher/* (differential input) */ 72*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 73*592f4aedSMax Krummenacher/* disable ddr pullups */ 74*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 75*592f4aedSMax KrummenacherDATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 76*592f4aedSMax Krummenacher/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 77*592f4aedSMax KrummenacherDATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 78*592f4aedSMax Krummenacher 79*592f4aedSMax Krummenacher/* Read data DQ Byte0-3 delay */ 80*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 81*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 82*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 83*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 84*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 85*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 86*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 87*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 88*592f4aedSMax Krummenacher 89*592f4aedSMax Krummenacher/* 90*592f4aedSMax Krummenacher * MDMISC mirroring interleaved (row/bank/col) 91*592f4aedSMax Krummenacher */ 92*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 93*592f4aedSMax Krummenacher 94*592f4aedSMax Krummenacher/* 95*592f4aedSMax Krummenacher * MDSCR con_req 96*592f4aedSMax Krummenacher */ 97*592f4aedSMax KrummenacherDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 98