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/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-11.rst19 | Fix Version | `a7eff3477`_ "fix(sdei): ensure that interrupt ID is valid" |
28 interrupt ID causes out of bound memory read.
30 SDEI_INTERRUPT_BIND is used to bind any physical interrupt into a normal
31 priority SDEI event. The interrupt can be a private peripheral interrupt
32 (PPI) or a shared peripheral interrupt (SPI).
35 The vulnerability exists when the SDEI client passes an interrupt ID which
44 sdei_interrupt_bind(interrupt ID)
45 -> plat_ic_get_interrupt_type(interrupt ID)
46 -> gicv2_get_interrupt_group(interrupt ID)
47 -> gicd_get_igroupr(distributor base, interrupt ID)
[all …]
/rk3399_ARM-atf/docs/components/
H A Dplatform-interrupt-controller-API.rst4 This document lists the optional platform interrupt controller API that
5 abstracts the runtime configuration and control of interrupt controller from the
17 This API should return the priority of the interrupt the PE is currently
18 servicing. This must be be called only after an interrupt has already been
22 is read to determine the priority of the interrupt.
32 The API should return whether the interrupt ID (first parameter) is categorized
45 The API should return whether the interrupt ID (first parameter) is categorized
58 The API should return whether the interrupt ID (first parameter) is categorized
71 This API should return the *active* status of the interrupt ID specified by the
76 interrupt.
[all …]
H A Dexception-handling.rst26 interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of
91 Arm GIC architecture defines it, although it's applied to non-interrupt
109 this is implicit when an interrupt is targeted and acknowledged at EL3, and the
110 priority of the acknowledged interrupt is used to match its registered handler.
111 The priority level is likewise implicitly deactivated when the interrupt
112 handling concludes by EOIing the interrupt.
114 Non-interrupt exceptions (SErrors, for example) don't have a notion of priority.
116 for these non-interrupt exceptions to assume a priority, and to interwork with
121 Because priority activation and deactivation for interrupt handling is implicit
123 interrupt to preempt a higher priority one. By extension, this means that a
[all …]
/rk3399_ARM-atf/fdts/
H A Dstm32mp151.dtsi6 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 intc: interrupt-controller@a0021000 {
34 #interrupt-cells = <3>;
35 interrupt-controller;
76 interrupt-parent = <&intc>;
129 interrupt-names = "event", "error";
203 secure-interrupt-names = "wakeup";
239 interrupt-controller;
240 #interrupt-cells = <3>;
243 exti: interrupt-controller@5000d000 {
[all …]
H A Dfvp-ve-Cortex-A7x1.dts7 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
50 gic: interrupt-controller@2c001000 {
52 #interrupt-cells = <3>;
54 interrupt-controller;
80 #interrupt-cells = <1>;
81 interrupt-map-mask = <0 0 63>;
82 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
H A Dstm32mp251.dtsi8 #include <dt-bindings/interrupt-controller/arm-gic.h>
59 intc: interrupt-controller@4ac00000 {
61 #interrupt-cells = <3>;
63 interrupt-controller;
72 interrupt-parent = <&intc>;
84 interrupt-parent = <&intc>;
369 interrupt-controller;
370 #interrupt-cells = <2>;
380 interrupt-controller;
381 #interrupt-cells = <2>;
[all …]
H A Dcorstone700.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
34 gic: interrupt-controller@1c000000 {
36 #interrupt-cells = <3>;
38 interrupt-controller;
76 interrupt-parent = <&gic>;
85 interrupt-parent = <&gic>;
120 interrupt-names = "mhu_rx";
132 interrupt-names = "mhu_rx";
144 interrupt-names = "mhu_rx";
H A Dn1sdp.dtsi6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
90 gic: interrupt-controller@30000000 {
93 #interrupt-cells = <3>;
96 interrupt-controller;
137 interrupt-names = "eventq", "cmdq-sync", "gerror";
149 interrupt-names = "eventq", "cmdq-sync", "gerror";
167 #interrupt-cells = <1>;
168 interrupt-map-mask = <0 0 0 7>;
169 interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dstm32mp131.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
61 intc: interrupt-controller@a0021000 {
63 #interrupt-cells = <3>;
64 interrupt-controller;
78 interrupt-parent = <&intc>;
172 interrupt-names = "event", "error";
187 interrupt-names = "event", "error";
202 interrupt-names = "event", "error";
223 secure-interrupt-names = "wakeup";
249 exti: interrupt-controller@5000d000 {
[all …]
H A Dfvp-base-gicv5.dtsi7 #include <dt-bindings/interrupt-controller/arm-gicv5.h>
12 gic: interrupt-controller {
15 #interrupt-cells = <3>;
16 interrupt-controller;
64 iwb0: interrupt-controller@2f000000 {
70 interrupt-controller;
71 #interrupt-cells = <2>;
80 interrupt-names = "phys", "virt", "hyp-phys";
100 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
148 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
H A Dfvp-base-gicv2.dtsi12 gic: interrupt-controller@2f000000 {
14 #interrupt-cells = <3>;
16 interrupt-controller;
H A Dmorello.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
20 gic: interrupt-controller@2c010000 {
23 #interrupt-cells = <3>;
26 interrupt-controller;
57 interrupt-names = "mhu_lpri_rx",
H A Dfvp-ve-Cortex-A5x1.dts7 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
70 gic: interrupt-controller@2c001000 {
72 #interrupt-cells = <3>;
74 interrupt-controller;
145 #interrupt-cells = <1>;
146 interrupt-map-mask = <0 0 63>;
147 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
H A Da5ds.dts12 interrupt-parent = <&gic>;
97 gic: interrupt-controller@1c001000 {
99 #interrupt-cells = <3>;
101 interrupt-controller;
110 interrupt-parent = <&gic>;
119 interrupt-parent = <&gic>;
150 interrupt-parent = <&gic>;
H A Dfvp-base-gicv3.dtsi12 gic: interrupt-controller@2f000000 {
14 #interrupt-cells = <3>;
18 interrupt-controller;
H A Dfvp-base-psci-common.dtsi18 interrupt-parent = <&gic>;
115 interrupt-parent = <&gic>;
134 #interrupt-cells = <1>;
135 interrupt-map-mask = <0 0 63>;
142 #interrupt-cells = <1>;
149 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
157 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
H A Darm_fpga.dts11 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
89 gic: interrupt-controller@30000000 {
92 #interrupt-cells = <3>;
95 interrupt-controller;
H A Dfvp-foundation-gicv2-psci.dts14 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 interrupt-parent = <&gic>;
92 gic: interrupt-controller@2f000000 {
94 #interrupt-cells = <3>;
96 interrupt-controller;
H A Dfvp-foundation-gicv3-psci.dts14 #include <dt-bindings/interrupt-controller/arm-gic.h>
25 interrupt-parent = <&gic>;
92 gic: interrupt-controller@2f000000 {
94 #interrupt-cells = <3>;
98 interrupt-controller;
H A Dcorstone700_fpga.dts18 interrupt-parent = <&gic>;
27 interrupt-parent = <&gic>;
H A Dtc-base.dtsi61 interrupt-parent = <&gic>;
270 interrupt-names = MHU_RX_INT_NAME;
279 interrupt-names = MHU_TX_INT_NAME;
308 gic: interrupt-controller@GIC_CTRL_ADDR {
311 #interrupt-cells = <4>;
314 interrupt-controller;
513 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
525 interrupt-names = "eventq", "cmdq-sync", "gerror";
537 interrupt-names = "eventq", "cmdq-sync", "gerror";
548 interrupt-names = "DPU";
[all …]
H A Dfvp-base-gicv23-interrupts.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 * terminology. Each interrupt property descriptor has 3 fields:
49 * 3. Type of interrupt (Edge or Level configured)
85 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
135 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
/rk3399_ARM-atf/docs/design/
H A Dinterrupt-framework-design.rst5 allows EL3 software to configure the interrupt routing behavior. Its main
11 the interrupt to either software in EL3 or Secure-EL1 depending upon the
32 The framework categorises an interrupt to be one of the following depending upon
35 #. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or
39 #. Non-secure interrupt. This type of interrupt can be routed to EL3,
44 #. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1
48 The following constants define the various interrupt types in the framework
60 A type of interrupt can be either generated as an FIQ or an IRQ. The target
61 exception level of an interrupt type is configured through the FIQ and IRQ bits
69 A routing model for a type of interrupt (generated as FIQ or IRQ) is defined as
[all …]
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_pm.c33 uint32_t interrupt = GIC_SPURIOUS_INTERRUPT; in stm32_cpu_standby() local
43 while (interrupt == GIC_SPURIOUS_INTERRUPT) { in stm32_cpu_standby()
47 interrupt = gicv2_acknowledge_interrupt(); in stm32_cpu_standby()
49 if ((interrupt != PENDING_G1_INTID) && in stm32_cpu_standby()
50 (interrupt != GIC_SPURIOUS_INTERRUPT)) { in stm32_cpu_standby()
51 gicv2_end_of_interrupt(interrupt); in stm32_cpu_standby()
/rk3399_ARM-atf/plat/intel/soc/common/fdts/
H A Dagilex5_fdt.dts14 interrupt-parent = <&gic>;
56 gic: interrupt-controller@2c010000 {
59 #interrupt-cells = <3>;
62 interrupt-controller;
71 interrupt-parent = <&gic>;

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