1/* 2 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <services/sdei_flags.h> 9 10#define SDEI_NORMAL 0x70 11#define HIGHEST_SEC 0 12 13/ { 14#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF 15 firmware { 16#if SDEI_IN_FCONF 17 sdei { 18 compatible = "arm,sdei-1.0"; 19 method = "smc"; 20 private_event_count = <3>; 21 shared_event_count = <3>; 22 /* 23 * Each event descriptor has typically 3 fields: 24 * 1. Event number 25 * 2. Interrupt number the event is bound to or 26 * if event is dynamic, specified as SDEI_DYN_IRQ 27 * 3. Bit map of event flags 28 */ 29 private_events = <1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 30 <1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 31 <1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 32 shared_events = <2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 33 <2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 34 <2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 35 }; 36#endif /* SDEI_IN_FCONF */ 37 38#if SEC_INT_DESC_IN_FCONF 39 sec_interrupts { 40 compatible = "arm,secure_interrupt_desc"; 41 /* Number of G0 and G1 secure interrupts defined by the platform */ 42 g0_intr_cnt = <2>; 43 g1s_intr_cnt = <9>; 44 /* 45 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 46 * terminology. Each interrupt property descriptor has 3 fields: 47 * 1. Interrupt number 48 * 2. Interrupt priority 49 * 3. Type of interrupt (Edge or Level configured) 50 */ 51 g0_intr_desc = < 8 SDEI_NORMAL EDGE>, 52 <14 HIGHEST_SEC EDGE>; 53 54 g1s_intr_desc = < 9 HIGHEST_SEC EDGE>, 55 <10 HIGHEST_SEC EDGE>, 56 <11 HIGHEST_SEC EDGE>, 57 <12 HIGHEST_SEC EDGE>, 58 <13 HIGHEST_SEC EDGE>, 59 <15 HIGHEST_SEC EDGE>, 60 <29 HIGHEST_SEC LEVEL>, 61 <56 HIGHEST_SEC LEVEL>, 62 <57 HIGHEST_SEC LEVEL>; 63 }; 64#endif /* SEC_INT_DESC_IN_FCONF */ 65 }; 66#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */ 67 timer { 68 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 69 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 72 }; 73 74 timer@2a810000 { 75 frame@2a830000 { 76 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 77 }; 78 }; 79 80 pmu { 81 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 82 }; 83 84 bus@8000000 { 85 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 86 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 87 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 88 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 89 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 90 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 91 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 92 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 93 <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 94 <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 95 <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 96 <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 97 <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 98 <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 99 <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 100 <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 101 <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 102 <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 103 <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 104 <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 105 <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 106 <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 107 <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 108 <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 109 <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 110 <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 111 <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 112 <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 113 <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 114 <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 115 <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 116 <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 117 <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 118 <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 119 <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 120 <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 121 <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 122 <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 123 <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 124 <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 125 <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 126 <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 127 <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 128 <0 0 43 &gic 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 129 <0 0 44 &gic 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 130 <0 0 46 &gic 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 131 }; 132 133#if (ENABLE_RME == 1) 134 pci: pci@40000000 { 135 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 136 <0 0 0 2 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 137 <0 0 0 3 &gic 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 138 <0 0 0 4 &gic 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 139 msi-map = <0x0 &its 0x0 0x10000>; 140 }; 141 142 smmu: iommu@2b400000 { 143 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 144 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 145 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 146 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; 147 msi-parent = <&its 0x10000>; 148 }; 149#endif /* ENABLE_RME */ 150}; 151