| #
62b56a72 |
| 22-Apr-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fdts: a5ds: Fix for the system timer issue." into integration
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| #
e3c152d1 |
| 17-Apr-2020 |
lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com> |
fdts: a5ds: Fix for the system timer issue.
A5DS FPGA system timer clock frequency is 7.5Mhz.
The dt is file updated inline with the hardware
clock frequency.
Change-Id: I3f6c2e0d4a7b293175a42cf398
fdts: a5ds: Fix for the system timer issue.
A5DS FPGA system timer clock frequency is 7.5Mhz.
The dt is file updated inline with the hardware
clock frequency.
Change-Id: I3f6c2e0d4a7b293175a42cf398a8730448504af9
Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com>
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|
| #
a3d0fa31 |
| 09-Mar-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fdts: a5ds: add ethernet node in devicetree" into integration
|
| #
c84cbf41 |
| 04-Mar-2020 |
Vishnu Banavath <vishnu.banavath@arm.com> |
fdts: a5ds: add ethernet node in devicetree
This change is to add ethernet and voltage regulator nodes into
a5ds devicetree.
Change-Id: If9ed67040d54e76af1813c9f99835f51f617e9df
Signed-off-by: Vish
fdts: a5ds: add ethernet node in devicetree
This change is to add ethernet and voltage regulator nodes into
a5ds devicetree.
Change-Id: If9ed67040d54e76af1813c9f99835f51f617e9df
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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|
| #
8849298c |
| 07-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "A5DS: Correct system freq, Cache Writeback Granule" into integration
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| #
786890ca |
| 18-Dec-2019 |
Avinash Mehta <avinash.mehta@arm.com> |
A5DS: Correct system freq, Cache Writeback Granule
Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeb
A5DS: Correct system freq, Cache Writeback Granule
Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeback
Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
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| #
90324ef4 |
| 19-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fdts: a5ds: cleanup enable-method in devicetree" into integration
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| #
f63e9f4c |
| 19-Dec-2019 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fdts: a5ds: add L2 cache node in devicetree" into integration
|
| #
ab3b00fb |
| 13-Dec-2019 |
Vishnu Banavath <vishnu.banavath@arm.com> |
fdts: a5ds: cleanup enable-method in devicetree
Same enable method is used by all the four cores. So,
make it globally for all the cores instead of adding
it to individual level.
Change-Id: I9b5728
fdts: a5ds: cleanup enable-method in devicetree
Same enable method is used by all the four cores. So,
make it globally for all the cores instead of adding
it to individual level.
Change-Id: I9b5728b0e0545c9e27160ea586009d929eb78cad
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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| #
79c6c342 |
| 13-Dec-2019 |
Vishnu Banavath <vishnu.banavath@arm.com> |
fdts: a5ds: add L2 cache node in devicetree
This change is to add L2 cache node into a5ds device tree.
Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947
Signed-off-by: Vishnu Banavath <vishnu.ba
fdts: a5ds: add L2 cache node in devicetree
This change is to add L2 cache node into a5ds device tree.
Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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| #
757d904b |
| 27-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "a5ds-multicore" into integration
* changes:
a5ds: add multicore support
a5ds: Hold the secondary cpus in pen rather than panic
|
| #
ec885bac |
| 19-Sep-2019 |
Usama Arif <usama.arif@arm.com> |
a5ds: add multicore support
Enable cores 1-3 using psci. On receiving the smc call from kernel,
core 0 will bring the secondary cores out pen and signal an event for
the cores. Currently on switchin
a5ds: add multicore support
Enable cores 1-3 using psci. On receiving the smc call from kernel,
core 0 will bring the secondary cores out pen and signal an event for
the cores. Currently on switching the cores is enabled i.e. it is not
possible to suspend, switch cores off, etc.
Change-Id: I6087e1d2ec650e1d587fd543efc1b08cbb50ae5f
Signed-off-by: Usama Arif <usama.arif@arm.com>
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| #
7a8ef89f |
| 17-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "plat/arm: Introduce A5 DesignStart platform." into integration
|
| #
00c7d5ac |
| 18-Jun-2019 |
Usama Arif <usama.arif@arm.com> |
plat/arm: Introduce A5 DesignStart platform.
This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.
Currently with
plat/arm: Introduce A5 DesignStart platform.
This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.
Currently with this patch only the primary CPU is booted
and the rest of them wait for an interrupt.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
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|