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Searched refs:cpu_id (Results 1 – 25 of 74) sorted by relevance

123

/rk3399_ARM-atf/plat/marvell/armada/a8k/common/
H A Dplat_pm.c90 #define PWRC_CPUN_CR_REG(cpu_id) \ argument
91 (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10))
100 #define CCU_B_PRCRN_REG(cpu_id) \ argument
102 ((cpu_id / 2) * (0x400)) + ((cpu_id % 2) * 4))
119 static int plat_marvell_cpu_powerdown(int cpu_id) in plat_marvell_cpu_powerdown() argument
124 INFO("Powering down CPU%d\n", cpu_id); in plat_marvell_cpu_powerdown()
127 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
129 mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); in plat_marvell_cpu_powerdown()
133 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
139 reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); in plat_marvell_cpu_powerdown()
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/rk3399_ARM-atf/plat/imx/imx8qx/
H A Dimx8qx_psci.c68 unsigned int cpu_id; in imx_pwr_domain_on() local
70 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_on()
72 printf("imx_pwr_domain_on cpu_id %d\n", cpu_id); in imx_pwr_domain_on()
74 if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], in imx_pwr_domain_on()
76 ERROR("core %d power on failed!\n", cpu_id); in imx_pwr_domain_on()
80 if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], in imx_pwr_domain_on()
82 ERROR("boot core %d failed!\n", cpu_id); in imx_pwr_domain_on()
103 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_off() local
106 sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], in imx_pwr_domain_off()
108 printf("turn off core:%d\n", cpu_id); in imx_pwr_domain_off()
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/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_smp.c54 int mt_smp_power_core_on(unsigned int cpu_id, struct cpu_pwr_ctrl *pwr_ctrl) in mt_smp_power_core_on() argument
64 GIC_WAKEUP_IGNORE(cpu_id)); in mt_smp_power_core_on()
65 mmio_setbits_32(SPM_EXT_INT_WAKEUP_REQ_SET, BIT(cpu_id)); in mt_smp_power_core_on()
68 SPMC_CPU_RESET_PWRON_CONFIG << (cpu_id)); in mt_smp_power_core_on()
73 DO_SMP_CORE_ON_WAIT_TIMEOUT(cpu_id, val); in mt_smp_power_core_on()
74 mmio_setbits_32(SPM_EXT_INT_WAKEUP_REQ_CLR, BIT(cpu_id)); in mt_smp_power_core_on()
77 SPMC_CPU_RESET_PWRON_CONFIG << (cpu_id)); in mt_smp_power_core_on()
79 __func__, __LINE__, cpu_id); in mt_smp_power_core_on()
85 int mt_smp_power_core_off(unsigned int cpu_id, struct cpu_pwr_ctrl *pwr_ctrl) in mt_smp_power_core_off() argument
88 GIC_WAKEUP_IGNORE(cpu_id)); in mt_smp_power_core_off()
/rk3399_ARM-atf/drivers/nxp/scmi/vendor/
H A Dscmi_imx9.h102 uint32_t cpu_id; member
113 uint32_t cpu_id; member
121 uint32_t cpu_id; member
135 uint32_t cpu_id; member
149 int scmi_core_set_reset_addr(void *p, uint64_t reset_addr, uint32_t cpu_id, uint32_t attr);
150 int scmi_core_start(void *p, uint32_t cpu_id);
151 int scmi_core_stop(void *p, uint32_t cpu_id);
152 int scmi_core_info_get(void *p, uint32_t cpu_id, uint32_t *run, uint32_t *sleep,
154 int scmi_core_set_sleep_mode(void *p, uint32_t cpu_id, uint32_t wakeup, uint32_t mode);
155 int scmi_core_Irq_wake_set(void *p, uint32_t cpu_id, uint32_t mask_idx,
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/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/pmu/
H A Dpmu.c124 static int cpus_power_domain_on(uint32_t cpu_id) in cpus_power_domain_on() argument
128 cpu_pd = PD_CPU0 + cpu_id; in cpus_power_domain_on()
134 BIT(cpu_id) | (BIT(cpu_id) << 16)); in cpus_power_domain_on()
142 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), BIT(cpu_id) << 16); in cpus_power_domain_on()
147 static int cpus_power_domain_off(uint32_t cpu_id) in cpus_power_domain_off() argument
149 uint32_t cpu_pd = PD_CPU0 + cpu_id; in cpus_power_domain_off()
154 if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK)) in cpus_power_domain_off()
159 BIT(cpu_id) | (BIT(cpu_id) << 16)); in cpus_power_domain_off()
194 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); in rockchip_soc_cores_pwr_dm_on() local
196 assert(cpu_id < PLATFORM_CORE_COUNT); in rockchip_soc_cores_pwr_dm_on()
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/rk3399_ARM-atf/plat/rockchip/common/
H A Dplat_topology.c24 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
26 cpu_id = mpidr & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
33 cpu_id += (cluster_id >> PLAT_RK_CLST_TO_CPUID_SHIFT); in plat_core_pos_by_mpidr()
35 if (cpu_id >= PLATFORM_CORE_COUNT) in plat_core_pos_by_mpidr()
38 return cpu_id; in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_psci.c33 void socfpga_wakeup_secondary_cpu(unsigned int cpu_id);
57 unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); in socfpga_pwr_domain_on() local
67 if (cpu_id == -1) in socfpga_pwr_domain_on()
71 if (cpu_id == 0x00) { in socfpga_pwr_domain_on()
77 mmio_write_64(PLAT_CPUID_RELEASE, cpu_id); in socfpga_pwr_domain_on()
86 if ((AGX5_PWRMGR_MPU_TRIGGER_PCH_CPU(1 << cpu_id) & (pch_cpu)) != 0) in socfpga_pwr_domain_on()
87 bl31_plat_reset_secondary_cpu(cpu_id); in socfpga_pwr_domain_on()
89 bl31_plat_set_secondary_cpu_entrypoint(cpu_id); in socfpga_pwr_domain_on()
91 mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); in socfpga_pwr_domain_on()
92 mmio_write_64(PLAT_CPUID_RELEASE, cpu_id); in socfpga_pwr_domain_on()
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H A Dsocfpga_topology.c29 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
37 cpu_id = (mpidr >> PLAT_CPU_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
46 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) in plat_core_pos_by_mpidr()
49 return (cpu_id + (cluster_id * 4)); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/renesas/common/
H A Dplat_topology.c26 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
34 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
39 if (cluster_id == 0 && cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT) in plat_core_pos_by_mpidr()
42 if (cluster_id == 1 && cpu_id >= PLATFORM_CLUSTER1_CORE_COUNT) in plat_core_pos_by_mpidr()
45 return (cpu_id + cluster_id * PLATFORM_CLUSTER0_CORE_COUNT); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c36 static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) in get_cpus_pwr_domain_cfg_info() argument
40 pd_reg = mmio_read_32(PMU_BASE + PMU_PWRDN_CON) & BIT(cpu_id); in get_cpus_pwr_domain_cfg_info()
41 apm_reg = mmio_read_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id)) & in get_cpus_pwr_domain_cfg_info()
54 static int cpus_power_domain_on(uint32_t cpu_id) in cpus_power_domain_on() argument
58 cpu_pd = PD_CPU0 + cpu_id; in cpus_power_domain_on()
59 cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id); in cpus_power_domain_on()
63 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
68 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
75 WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id); in cpus_power_domain_on()
79 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
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/rk3399_ARM-atf/plat/xilinx/versal_net/include/
H A Dversal_net_def.h77 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \ argument
78 (APU_PCLI_CPU_STEP * (cpu_id))))
81 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \ argument
82 (APU_PCLI_CPU_STEP * (cpu_id))))
85 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \ argument
86 (APU_PCLI_CPU_STEP * (cpu_id))))
89 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \ argument
90 (APU_PCLI_CPU_STEP * (cpu_id))))
93 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ argument
94 (APU_PCLI_CPU_STEP * (cpu_id))))
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/rk3399_ARM-atf/plat/amd/versal2/include/
H A Ddef.h82 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \ argument
83 (APU_PCLI_CPU_STEP * (cpu_id))))
86 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \ argument
87 (APU_PCLI_CPU_STEP * (cpu_id))))
90 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \ argument
91 (APU_PCLI_CPU_STEP * (cpu_id))))
94 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \ argument
95 (APU_PCLI_CPU_STEP * (cpu_id))))
98 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ argument
99 (APU_PCLI_CPU_STEP * (cpu_id))))
102 APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) global() argument
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/rk3399_ARM-atf/plat/nvidia/tegra/drivers/flowctrl/
H A Dflowctrl.c47 static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val) in tegra_fc_cc4_ctrl() argument
49 mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val); in tegra_fc_cc4_ctrl()
50 val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]); in tegra_fc_cc4_ctrl()
53 static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val) in tegra_fc_cpu_csr() argument
55 mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val); in tegra_fc_cpu_csr()
56 val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]); in tegra_fc_cpu_csr()
59 static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val) in tegra_fc_halt_cpu() argument
61 mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val); in tegra_fc_halt_cpu()
62 val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]); in tegra_fc_halt_cpu()
65 static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr) in tegra_fc_prepare_suspend() argument
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/rk3399_ARM-atf/plat/imx/imx8qm/
H A Dimx8qm_psci.c78 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_on() local
87 ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], in imx_pwr_domain_on()
89 ERROR("core %d power on failed!\n", cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id); in imx_pwr_domain_on()
94 ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], in imx_pwr_domain_on()
96 ERROR("boot core %d failed!\n", cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id); in imx_pwr_domain_on()
118 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_off() local
122 ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], in imx_pwr_domain_off()
130 printf("turn off cluster:%d core:%d\n", cluster_id, cpu_id); in imx_pwr_domain_off()
137 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend() local
142 ap_core_index[cpu_id + PLATFORM_CLUSTER0_CORE_COUNT * cluster_id], in imx_domain_suspend()
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/rk3399_ARM-atf/plat/nuvoton/common/
H A Dnuvoton_topology.c34 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
43 cpu_id = (unsigned int)MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
46 cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER) { in plat_core_pos_by_mpidr()
50 return (int)(cpu_id + (cluster_id * 4)); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/imx/common/
H A Dimx8_topology.c25 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
33 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
36 cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER) in plat_core_pos_by_mpidr()
39 return (cpu_id + (cluster_id * 4)); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/arm/board/a5ds/
H A Da5ds_topology.c31 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
39 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
48 if (cpu_id >= A5DS_MAX_CPUS_PER_CLUSTER) in plat_core_pos_by_mpidr()
51 return (cpu_id + (cluster_id * 4)); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/aspeed/ast2700/
H A Dplat_topology.c23 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
32 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
38 if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) { in plat_core_pos_by_mpidr()
42 return (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER) + cpu_id; in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_topology.c45 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
62 if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) in plat_core_pos_by_mpidr()
65 return (cpu_id + (cluster_id * 4)); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_topology.c45 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
62 if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) in plat_core_pos_by_mpidr()
65 return (cpu_id + (cluster_id * 4)); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/mediatek/mt8173/
H A Dplat_topology.c39 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
56 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) in plat_core_pos_by_mpidr()
59 return (cpu_id + (cluster_id * 4)); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dplat_topology.c38 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
46 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
55 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) in plat_core_pos_by_mpidr()
58 return (cpu_id + (cluster_id * 4)); in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dstm32mp2_topology.c32 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
42 cpu_id = (mpidr_copy >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
52 if (cpu_id >= PLATFORM_CORE_COUNT) { in plat_core_pos_by_mpidr()
56 return (int)cpu_id; in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_topology.c32 unsigned int cluster_id, cpu_id; in plat_core_pos_by_mpidr() local
42 cpu_id = (mpidr_copy >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
52 if (cpu_id >= PLATFORM_CORE_COUNT) { in plat_core_pos_by_mpidr()
56 return (int)cpu_id; in plat_core_pos_by_mpidr()
/rk3399_ARM-atf/plat/amd/versal2/
H A Dplat_psci_pm.c36 int32_t cpu_id = plat_core_pos_by_mpidr(mpidr); in versal2_pwr_domain_on() local
41 if (cpu_id != -1) { in versal2_pwr_domain_on()
42 proc = pm_get_proc((uint32_t)cpu_id); in versal2_pwr_domain_on()
67 uint32_t cpu_id = plat_my_core_pos(); in versal2_pwr_domain_off() local
71 proc = pm_get_proc(cpu_id); in versal2_pwr_domain_off()
73 ERROR("Failed to get proc %d\n", cpu_id); in versal2_pwr_domain_off()
95 ERROR("Failed to power down CPU %d\n", cpu_id); in versal2_pwr_domain_off()
157 uint32_t cpu_id = plat_my_core_pos(); in versal2_pwr_domain_suspend() local
162 proc = pm_get_proc(cpu_id); in versal2_pwr_domain_suspend()
164 ERROR("Failed to get proc %d\n", cpu_id); in versal2_pwr_domain_suspend()
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