Merge "fix(versal2): enable graceful system shutdown" into integration

fix(versal2): enable graceful system shutdown

Power down the APU cores before sending SYSTEM_SHUTDOWN call to
PLM firmware. This ensures graceful system shutdown.

Change-Id: I89a132e72c9a2530620ffb

fix(versal2): enable graceful system shutdown

Power down the APU cores before sending SYSTEM_SHUTDOWN call to
PLM firmware. This ensures graceful system shutdown.

Change-Id: I89a132e72c9a2530620ffb58aaec752796d01d3e
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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Merge changes from topic "xlnx_subsystem_restart_fix_versal2" into integration

* changes:
fix(versal2): handle debugfs specific APIs before EEMI handler
fix(versal2): use PM_STATE_CPU_OFF for co

Merge changes from topic "xlnx_subsystem_restart_fix_versal2" into integration

* changes:
fix(versal2): handle debugfs specific APIs before EEMI handler
fix(versal2): use PM_STATE_CPU_OFF for core power down in SELF_SUSPEND

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fix(versal2): use PM_STATE_CPU_OFF for core power down in SELF_SUSPEND

Currently TF-A provides PM_STATE_CPU_IDLE state during SELF_SUSPEND
to power down the core. PM_STATE_CPU_IDLE is intended for C

fix(versal2): use PM_STATE_CPU_OFF for core power down in SELF_SUSPEND

Currently TF-A provides PM_STATE_CPU_IDLE state during SELF_SUSPEND
to power down the core. PM_STATE_CPU_IDLE is intended for CPU-idle
suspend paths (when Linux CPU idle is enabled) and is not the correct
state for a full core power-off.

Fix this by providing PM_STATE_CPU_OFF state to power down the core.

Change-Id: I25585b32fe90372b0404a1ad89544f1aaa2f34a2
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG

Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG for psci

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fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was

fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was passed to the firmware which is incorrect. Pass NON_SECURE
flag from the platform specific file to the firmware in order to
align with the PSCI specification.

Change-Id: Iabe2cb45467cf63fe36626d323513ff05548eb3b
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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Merge changes from topic "xlnx_fix_plat_ns_entry" into integration

* changes:
feat(versal2): validate non-secure entry addr
feat(versal2): parse reserve memory subnodes

feat(versal2): validate non-secure entry addr

Added validate_ns_entrypoint to get reserved-memory entries from
the Flattened Device Tree (FDT). Identifies secure and non-secure
memory regions and ch

feat(versal2): validate non-secure entry addr

Added validate_ns_entrypoint to get reserved-memory entries from
the Flattened Device Tree (FDT). Identifies secure and non-secure
memory regions and checks if entry point lies within a valid
non-secure region.

Change-Id: Iff998fe855f5de8fbd96f0d7d4b0d7c33c904d34
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge "fix(xilinx): add API to get powerdown request status" into integration

fix(xilinx): add API to get powerdown request status

The pwrdwn_req_received variable is used across multiple platforms
through extern keyword. Instead of using the extern, add getter
API to access

fix(xilinx): add API to get powerdown request status

The pwrdwn_req_received variable is used across multiple platforms
through extern keyword. Instead of using the extern, add getter
API to access this variable across the platforms, and restrict the
scope of variable to the particular file by defining it as static
variable. This prevents unintended access of variable from other
files and increase safety.

Change-Id: I758466ea7f6be2a90ec249dc3e4fa56cdbe11e57
Signed-off-by: Devanshi Chauhan <devanshi.chauhanalpeshbhai@amd.com>

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Merge "fix(versal2): enable system reset" into integration

fix(versal2): enable system reset

The commit 414cf08b76bc ("feat(versal2): add support for platform
management") changed how system reset works by requiring
pwrdwn_req_received to be set for TF-A to

fix(versal2): enable system reset

The commit 414cf08b76bc ("feat(versal2): add support for platform
management") changed how system reset works by requiring
pwrdwn_req_received to be set for TF-A to make a call to PLM firmware.

This accidentally blocked reset initiated by Linux or U-Boot,
as this flag is only set during PLM firmware initiated reset.

Fix this issue by enabling firmware call when pwrdwn_req_received
is not set, ensuring Linux and U-Boot can initiate reset properly.

Fixes: 414cf08b76bc ("feat(versal2): add support for platform management")
Change-Id: I6ffc9b2efa56a7bd843b296e2c892c064ffd054a
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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Merge changes from topic "versal2-pm-support" into integration

* changes:
feat(versal2): extended SMCCC payload for EEMI
feat(versal2): add support for platform management
feat(versal2): add d

Merge changes from topic "versal2-pm-support" into integration

* changes:
feat(versal2): extended SMCCC payload for EEMI
feat(versal2): add support for platform management
feat(versal2): add dependency macro for PM

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feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM func

feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM functionality. Enable wakeup for
new peripherals

Change-Id: I1bf67dc46af91ee113c627d32ae6ecc1dad386c2
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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