xref: /rk3399_ARM-atf/plat/intel/soc/common/socfpga_topology.c (revision 3393060cfd1e4c6f3ab2e914a0e0787c2a81c37b)
1d8820789SHadi Asyrafi /*
2d8820789SHadi Asyrafi  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3d8820789SHadi Asyrafi  *
4d8820789SHadi Asyrafi  * SPDX-License-Identifier: BSD-3-Clause
5d8820789SHadi Asyrafi  */
6d8820789SHadi Asyrafi 
7d8820789SHadi Asyrafi #include <arch.h>
8d8820789SHadi Asyrafi #include <platform_def.h>
9d8820789SHadi Asyrafi #include <lib/psci/psci.h>
10d8820789SHadi Asyrafi 
11d8820789SHadi Asyrafi static const unsigned char plat_power_domain_tree_desc[] = {1, 4};
12d8820789SHadi Asyrafi 
13d8820789SHadi Asyrafi /*******************************************************************************
14d8820789SHadi Asyrafi  * This function returns the default topology tree information.
15d8820789SHadi Asyrafi  ******************************************************************************/
plat_get_power_domain_tree_desc(void)16d8820789SHadi Asyrafi const unsigned char *plat_get_power_domain_tree_desc(void)
17d8820789SHadi Asyrafi {
18d8820789SHadi Asyrafi 	return plat_power_domain_tree_desc;
19d8820789SHadi Asyrafi }
20d8820789SHadi Asyrafi 
21d8820789SHadi Asyrafi /*******************************************************************************
22d8820789SHadi Asyrafi  * This function implements a part of the critical interface between the psci
23d8820789SHadi Asyrafi  * generic layer and the platform that allows the former to query the platform
24d8820789SHadi Asyrafi  * to convert an MPIDR to a unique linear index. An error code (-1) is returned
25d8820789SHadi Asyrafi  * in case the MPIDR is invalid.
26d8820789SHadi Asyrafi  ******************************************************************************/
plat_core_pos_by_mpidr(u_register_t mpidr)27d8820789SHadi Asyrafi int plat_core_pos_by_mpidr(u_register_t mpidr)
28d8820789SHadi Asyrafi {
29d8820789SHadi Asyrafi 	unsigned int cluster_id, cpu_id;
30d8820789SHadi Asyrafi 
31d8820789SHadi Asyrafi 	mpidr &= MPIDR_AFFINITY_MASK;
32d8820789SHadi Asyrafi 
33d8820789SHadi Asyrafi 	if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
34d8820789SHadi Asyrafi 		return -1;
35d8820789SHadi Asyrafi 
36*79626f46SJit Loon Lim 	cluster_id = (mpidr >> PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK;
37*79626f46SJit Loon Lim 	cpu_id = (mpidr >> PLAT_CPU_ID_MPIDR_AFF_SHIFT) & MPIDR_AFFLVL_MASK;
38d8820789SHadi Asyrafi 
39d8820789SHadi Asyrafi 	if (cluster_id >= PLATFORM_CLUSTER_COUNT)
40d8820789SHadi Asyrafi 		return -1;
41d8820789SHadi Asyrafi 
42d8820789SHadi Asyrafi 	/*
43d8820789SHadi Asyrafi 	 * Validate cpu_id by checking whether it represents a CPU in
44d8820789SHadi Asyrafi 	 * one of the two clusters present on the platform.
45d8820789SHadi Asyrafi 	 */
46d8820789SHadi Asyrafi 	if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
47d8820789SHadi Asyrafi 		return -1;
48d8820789SHadi Asyrafi 
49d8820789SHadi Asyrafi 	return (cpu_id + (cluster_id * 4));
50d8820789SHadi Asyrafi }
51d8820789SHadi Asyrafi 
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