| #
ccd580c4 |
| 16-Sep-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration
* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat
Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration
* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat(stm32mp2): add RISAB registers description
feat(stm32mp2-fdts): add BL31 info in fw-config
feat(stm32mp2): add minimal support for BL31
feat(st): manage BL31 FCONF load_info struct
show more ...
|
| #
03020b66 |
| 13-Jun-2023 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32mp2): add minimal support for BL31
Add the required files to compile BL31 on STM32MP2.
Update BL2 configuration to load BL31. The platform boots until BL31,
but stops here as no other bina
feat(stm32mp2): add minimal support for BL31
Add the required files to compile BL31 on STM32MP2.
Update BL2 configuration to load BL31. The platform boots until BL31,
but stops here as no other binaries are loaded as DDR is not
initialized.
At runtime, BL31 will use only the first half of the SYSRAM, the upper
half will be used for non-secure DMA LLIs. To be sure nothing from this
area is still in the cache, invalidate the upper SYSRAM before enabling
BL31 cache. BL31 should then map only first half of the SYSRAM. But it
must temporarily map the upper half read-only, as this is where we will
retrieve BL2 parameters, used to fill registers for next boot stages.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ie91527a7a26625624b4b3c65fb6a0ca9dd355dbd
show more ...
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