124 static int cpus_power_domain_on(uint32_t cpu_id)  in cpus_power_domain_on()  argument
128 	cpu_pd = PD_CPU0 + cpu_id;  in cpus_power_domain_on()
134 			      BIT(cpu_id) | (BIT(cpu_id) << 16));  in cpus_power_domain_on()
142 	mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), BIT(cpu_id) << 16);  in cpus_power_domain_on()
147 static int cpus_power_domain_off(uint32_t cpu_id)  in cpus_power_domain_off()  argument
149 	uint32_t cpu_pd = PD_CPU0 + cpu_id;  in cpus_power_domain_off()
154 	if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK))  in cpus_power_domain_off()
159 		      BIT(cpu_id) | (BIT(cpu_id) << 16));  in cpus_power_domain_off()
194 	uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);  in rockchip_soc_cores_pwr_dm_on()  local
196 	assert(cpu_id < PLATFORM_CORE_COUNT);  in rockchip_soc_cores_pwr_dm_on()
197 	assert(cpuson_flags[cpu_id] == 0);  in rockchip_soc_cores_pwr_dm_on()
198 	cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG;  in rockchip_soc_cores_pwr_dm_on()
199 	cpuson_entry_point[cpu_id] = entrypoint;  in rockchip_soc_cores_pwr_dm_on()
202 	cpus_power_domain_on(cpu_id);  in rockchip_soc_cores_pwr_dm_on()