17d116dccSCC Ma /* 27d116dccSCC Ma * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 37d116dccSCC Ma * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 57d116dccSCC Ma */ 67d116dccSCC Ma 7*09d40e0eSAntonio Nino Diaz #include <platform_def.h> 8*09d40e0eSAntonio Nino Diaz 9*09d40e0eSAntonio Nino Diaz #include <arch.h> 10*09d40e0eSAntonio Nino Diaz #include <lib/psci/psci.h> 113fc26aa0SKoan-Sin Tan 123fc26aa0SKoan-Sin Tan const unsigned char mtk_power_domain_tree_desc[] = { 133fc26aa0SKoan-Sin Tan /* No of root nodes */ 143fc26aa0SKoan-Sin Tan PLATFORM_SYSTEM_COUNT, 153fc26aa0SKoan-Sin Tan /* No of children for the root node */ 163fc26aa0SKoan-Sin Tan PLATFORM_CLUSTER_COUNT, 173fc26aa0SKoan-Sin Tan /* No of children for the first cluster node */ 183fc26aa0SKoan-Sin Tan PLATFORM_CLUSTER0_CORE_COUNT, 193fc26aa0SKoan-Sin Tan /* No of children for the second cluster node */ 203fc26aa0SKoan-Sin Tan PLATFORM_CLUSTER1_CORE_COUNT 213fc26aa0SKoan-Sin Tan }; 223fc26aa0SKoan-Sin Tan 233fc26aa0SKoan-Sin Tan /******************************************************************************* 243fc26aa0SKoan-Sin Tan * This function returns the MT8173 default topology tree information. 253fc26aa0SKoan-Sin Tan ******************************************************************************/ plat_get_power_domain_tree_desc(void)263fc26aa0SKoan-Sin Tanconst unsigned char *plat_get_power_domain_tree_desc(void) 273fc26aa0SKoan-Sin Tan { 283fc26aa0SKoan-Sin Tan return mtk_power_domain_tree_desc; 293fc26aa0SKoan-Sin Tan } 303fc26aa0SKoan-Sin Tan 313fc26aa0SKoan-Sin Tan /******************************************************************************* 323fc26aa0SKoan-Sin Tan * This function implements a part of the critical interface between the psci 333fc26aa0SKoan-Sin Tan * generic layer and the platform that allows the former to query the platform 343fc26aa0SKoan-Sin Tan * to convert an MPIDR to a unique linear index. An error code (-1) is returned 353fc26aa0SKoan-Sin Tan * in case the MPIDR is invalid. 363fc26aa0SKoan-Sin Tan ******************************************************************************/ plat_core_pos_by_mpidr(u_register_t mpidr)373fc26aa0SKoan-Sin Tanint plat_core_pos_by_mpidr(u_register_t mpidr) 383fc26aa0SKoan-Sin Tan { 393fc26aa0SKoan-Sin Tan unsigned int cluster_id, cpu_id; 403fc26aa0SKoan-Sin Tan 413fc26aa0SKoan-Sin Tan mpidr &= MPIDR_AFFINITY_MASK; 423fc26aa0SKoan-Sin Tan 433fc26aa0SKoan-Sin Tan if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) 443fc26aa0SKoan-Sin Tan return -1; 453fc26aa0SKoan-Sin Tan 463fc26aa0SKoan-Sin Tan cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 473fc26aa0SKoan-Sin Tan cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 483fc26aa0SKoan-Sin Tan 493fc26aa0SKoan-Sin Tan if (cluster_id >= PLATFORM_CLUSTER_COUNT) 503fc26aa0SKoan-Sin Tan return -1; 513fc26aa0SKoan-Sin Tan 523fc26aa0SKoan-Sin Tan /* 533fc26aa0SKoan-Sin Tan * Validate cpu_id by checking whether it represents a CPU in 543fc26aa0SKoan-Sin Tan * one of the two clusters present on the platform. 553fc26aa0SKoan-Sin Tan */ 563fc26aa0SKoan-Sin Tan if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) 573fc26aa0SKoan-Sin Tan return -1; 583fc26aa0SKoan-Sin Tan 593fc26aa0SKoan-Sin Tan return (cpu_id + (cluster_id * 4)); 603fc26aa0SKoan-Sin Tan } 61