1*03020b66SYann Gautier /* 2*03020b66SYann Gautier * Copyright (c) 2024, STMicroelectronics - All Rights Reserved 3*03020b66SYann Gautier * 4*03020b66SYann Gautier * SPDX-License-Identifier: BSD-3-Clause 5*03020b66SYann Gautier */ 6*03020b66SYann Gautier 7*03020b66SYann Gautier #include <lib/psci/psci.h> 8*03020b66SYann Gautier #include <plat/common/platform.h> 9*03020b66SYann Gautier 10*03020b66SYann Gautier #include <platform_def.h> 11*03020b66SYann Gautier 12*03020b66SYann Gautier /* 1 cluster, all cores into */ 13*03020b66SYann Gautier static const unsigned char stm32mp2_power_domain_tree_desc[] = { 14*03020b66SYann Gautier PLATFORM_CLUSTER_COUNT, 15*03020b66SYann Gautier PLATFORM_CORE_COUNT, 16*03020b66SYann Gautier }; 17*03020b66SYann Gautier 18*03020b66SYann Gautier /* This function returns the platform topology */ plat_get_power_domain_tree_desc(void)19*03020b66SYann Gautierconst unsigned char *plat_get_power_domain_tree_desc(void) 20*03020b66SYann Gautier { 21*03020b66SYann Gautier return stm32mp2_power_domain_tree_desc; 22*03020b66SYann Gautier } 23*03020b66SYann Gautier 24*03020b66SYann Gautier /******************************************************************************* 25*03020b66SYann Gautier * This function implements a part of the critical interface between the psci 26*03020b66SYann Gautier * generic layer and the platform that allows the former to query the platform 27*03020b66SYann Gautier * to convert an MPIDR to a unique linear index. An error code (-1) is returned 28*03020b66SYann Gautier * in case the MPIDR is invalid. 29*03020b66SYann Gautier ******************************************************************************/ plat_core_pos_by_mpidr(u_register_t mpidr)30*03020b66SYann Gautierint plat_core_pos_by_mpidr(u_register_t mpidr) 31*03020b66SYann Gautier { 32*03020b66SYann Gautier unsigned int cluster_id, cpu_id; 33*03020b66SYann Gautier u_register_t mpidr_copy = mpidr; 34*03020b66SYann Gautier 35*03020b66SYann Gautier mpidr_copy &= MPIDR_AFFINITY_MASK; 36*03020b66SYann Gautier 37*03020b66SYann Gautier if ((mpidr_copy & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0U) { 38*03020b66SYann Gautier return -1; 39*03020b66SYann Gautier } 40*03020b66SYann Gautier 41*03020b66SYann Gautier cluster_id = (mpidr_copy >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 42*03020b66SYann Gautier cpu_id = (mpidr_copy >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 43*03020b66SYann Gautier 44*03020b66SYann Gautier if (cluster_id >= PLATFORM_CLUSTER_COUNT) { 45*03020b66SYann Gautier return -1; 46*03020b66SYann Gautier } 47*03020b66SYann Gautier 48*03020b66SYann Gautier /* 49*03020b66SYann Gautier * Validate cpu_id by checking whether it represents a CPU in one 50*03020b66SYann Gautier * of the two clusters present on the platform. 51*03020b66SYann Gautier */ 52*03020b66SYann Gautier if (cpu_id >= PLATFORM_CORE_COUNT) { 53*03020b66SYann Gautier return -1; 54*03020b66SYann Gautier } 55*03020b66SYann Gautier 56*03020b66SYann Gautier return (int)cpu_id; 57*03020b66SYann Gautier } 58