1bd08def3SAnson Huang /* 2bd08def3SAnson Huang * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3bd08def3SAnson Huang * 4bd08def3SAnson Huang * SPDX-License-Identifier: BSD-3-Clause 5bd08def3SAnson Huang */ 6bd08def3SAnson Huang 7bd08def3SAnson Huang #include <arch.h> 8bd08def3SAnson Huang #include <arch_helpers.h> 9*09d40e0eSAntonio Nino Diaz #include <plat/common/platform.h> 10bd08def3SAnson Huang 11bd08def3SAnson Huang const unsigned char imx_power_domain_tree_desc[] = { 12bd08def3SAnson Huang PWR_DOMAIN_AT_MAX_LVL, 13bd08def3SAnson Huang PLATFORM_CLUSTER_COUNT, 140f53bca0SAnson Huang PLATFORM_CLUSTER0_CORE_COUNT, 150f53bca0SAnson Huang PLATFORM_CLUSTER1_CORE_COUNT, 16bd08def3SAnson Huang }; 17bd08def3SAnson Huang plat_get_power_domain_tree_desc(void)18bd08def3SAnson Huangconst unsigned char *plat_get_power_domain_tree_desc(void) 19bd08def3SAnson Huang { 20bd08def3SAnson Huang return imx_power_domain_tree_desc; 21bd08def3SAnson Huang } 22bd08def3SAnson Huang plat_core_pos_by_mpidr(u_register_t mpidr)23bd08def3SAnson Huangint plat_core_pos_by_mpidr(u_register_t mpidr) 24bd08def3SAnson Huang { 25bd08def3SAnson Huang unsigned int cluster_id, cpu_id; 26bd08def3SAnson Huang 27bd08def3SAnson Huang mpidr &= MPIDR_AFFINITY_MASK; 28bd08def3SAnson Huang 29bd08def3SAnson Huang if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) 30bd08def3SAnson Huang return -1; 31bd08def3SAnson Huang 32bd08def3SAnson Huang cluster_id = MPIDR_AFFLVL1_VAL(mpidr); 33bd08def3SAnson Huang cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 34bd08def3SAnson Huang 35bd08def3SAnson Huang if (cluster_id > PLATFORM_CLUSTER_COUNT || 36bd08def3SAnson Huang cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER) 37bd08def3SAnson Huang return -1; 38bd08def3SAnson Huang 39bd08def3SAnson Huang return (cpu_id + (cluster_id * 4)); 40bd08def3SAnson Huang } 41