| /rk3399_ARM-atf/services/spd/trusty/ |
| H A D | generic-arm64-smcall.c | 20 #define PLAT_ARM_GICR_BASE GICR_BASE macro
27 #ifndef PLAT_ARM_GICR_BASE
28 #define PLAT_ARM_GICR_BASE SMC_UNK macro
74 return PLAT_ARM_GICR_BASE; in trusty_get_reg_base()
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| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdn2/ |
| H A D | rdn2_plat.c | 113 PLAT_ARM_GICR_BASE,
117 PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
121 PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
125 PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
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| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/ |
| H A D | rdv3_bl31_setup.c | 136 PLAT_ARM_GICR_BASE,
140 PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
144 PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
148 PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
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| /rk3399_ARM-atf/plat/arm/board/n1sdp/ |
| H A D | n1sdp_bl31_setup.c | 67 PLAT_ARM_GICR_BASE,
68 PLAT_ARM_GICR_BASE + PLAT_ARM_REMOTE_CHIP_OFFSET,
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| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd2/ |
| H A D | nrd_plat_arm_def2.h | 221 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00100000) macro
223 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00300000) macro
225 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x001C0000) macro
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| /rk3399_ARM-atf/plat/renesas/rcar_gen4/ |
| H A D | bl31_plat_setup.c | 61 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
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| /rk3399_ARM-atf/plat/xilinx/versal/ |
| H A D | versal_gicv3.c | 66 .gicr_base = PLAT_ARM_GICR_BASE,
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| /rk3399_ARM-atf/plat/arm/board/fvp/ |
| H A D | fvp_gicv3.c | 92 arm_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE; in fvp_gic_driver_pre_init()
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| /rk3399_ARM-atf/plat/xilinx/versal/include/ |
| H A D | platform_def.h | 125 #define PLAT_ARM_GICR_BASE U(0xF9080000) macro
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| H A D | plat_macros.S | 107 mov_imm x16, PLAT_ARM_GICR_BASE
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| /rk3399_ARM-atf/plat/renesas/rcar_gen5/include/ |
| H A D | rcar_def.h | 64 #define PLAT_ARM_GICR_BASE UL(0x38080000) macro
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| /rk3399_ARM-atf/plat/amd/versal2/include/ |
| H A D | platform_def.h | 128 #define PLAT_ARM_GICR_BASE PLAT_GICR_BASE_VALUE macro
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| /rk3399_ARM-atf/plat/imx/imx9/imx95/include/ |
| H A D | platform_def.h | 45 #define PLAT_ARM_GICR_BASE PLAT_GICR_BASE macro
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| /rk3399_ARM-atf/plat/imx/imx9/imx94/include/ |
| H A D | platform_def.h | 43 #define PLAT_ARM_GICR_BASE PLAT_GICR_BASE macro
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| /rk3399_ARM-atf/plat/xilinx/versal_net/include/ |
| H A D | platform_def.h | 121 #define PLAT_ARM_GICR_BASE U(0xE2060000) macro
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| /rk3399_ARM-atf/plat/renesas/rcar_gen4/include/ |
| H A D | rcar_def.h | 71 #define PLAT_ARM_GICR_BASE UL(0xF1060000) macro
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| /rk3399_ARM-atf/plat/renesas/rcar_gen5/ |
| H A D | bl31_plat_setup.c | 151 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
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| /rk3399_ARM-atf/plat/imx/imx9/common/ |
| H A D | imx9_bl31_setup.c | 119 gic_data.gicr_base = PLAT_ARM_GICR_BASE; in bl31_platform_setup()
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| /rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rd1ae/include/ |
| H A D | platform_def.h | 68 #define PLAT_ARM_GICR_BASE UL(0x301C0000) macro
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| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/ |
| H A D | nrd_plat_arm_def3.h | 305 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00100000) macro
307 #define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x001C0000) macro
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| /rk3399_ARM-atf/plat/arm/common/sp_min/ |
| H A D | arm_sp_min_setup.c | 26 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
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| /rk3399_ARM-atf/plat/arm/board/morello/include/ |
| H A D | platform_def.h | 248 #define PLAT_ARM_GICR_BASE UL(0x300C0000) macro
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| /rk3399_ARM-atf/plat/arm/board/n1sdp/include/ |
| H A D | platform_def.h | 276 #define PLAT_ARM_GICR_BASE 0x300C0000 macro
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| /rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rdaspen/include/ |
| H A D | platform_def.h | 126 #define PLAT_ARM_GICR_BASE UL(0x200C0000) macro
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| /rk3399_ARM-atf/plat/xilinx/versal_net/ |
| H A D | bl31_versal_net_setup.c | 34 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
|