Merge "refactor(arm): remove unused SP_MIN UART macros" into integration

refactor(arm): remove unused SP_MIN UART macros

Currently, tf-a has been refactored to support the multi UARTs (boot and
runtime UARTs). As a result, the SP_MIN UART related code has been
removed, a

refactor(arm): remove unused SP_MIN UART macros

Currently, tf-a has been refactored to support the multi UARTs (boot and
runtime UARTs). As a result, the SP_MIN UART related code has been
removed, and the macros are no longer used.

Therefore, this patch removes these unused UART macros.

Change-Id: I496349f876ba918fcafa7ed6c65d149914762290
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "DPE" into integration

* changes:
feat(tc): add RSS SDS region right after SCMI payload
refactor(n1sdp): update SDS driver calls
refactor(morello): update SDS driver c

Merge changes from topic "DPE" into integration

* changes:
feat(tc): add RSS SDS region right after SCMI payload
refactor(n1sdp): update SDS driver calls
refactor(morello): update SDS driver calls
refactor(juno): update SDS driver calls
refactor(sgi): update SDS driver calls
refactor(css): support multiple SDS regions

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refactor(n1sdp): update SDS driver calls

Update SDS driver calls to align with recent
changes [1] of the SDS driver.

- The driver now requires us to explicitly pass
the SDS region id to act on.
-

refactor(n1sdp): update SDS driver calls

Update SDS driver calls to align with recent
changes [1] of the SDS driver.

- The driver now requires us to explicitly pass
the SDS region id to act on.
- Implement plat_sds_get_regions() platform function
which is used by the driver to get SDS region
information per platform.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/24609/

Change-Id: I3447855fbe7427376d5f7aa0ba7356fe2f14d567
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>

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Merge "fix(n1sdp): configure platform specific secure SPIs" into integration

fix(n1sdp): configure platform specific secure SPIs

Previous implementation used common CSS interrupts, which do not match
the N1SDP platform interrupt map. Updated to configure Secure
interrupts ac

fix(n1sdp): configure platform specific secure SPIs

Previous implementation used common CSS interrupts, which do not match
the N1SDP platform interrupt map. Updated to configure Secure
interrupts according to the N1SDP TRM and InfraSYSDESIGN4.0
specification. Additionally, unused definitions from legacy interrupt
configuration are removed.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I3dd4bcd4875e138057c62d937572d446b8f88471

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Merge changes I366740a9,I533abdd6,I6aa3b6dc into integration

* changes:
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
fix(n1sdp): add numa node id for pcie controllers
fix(n1sdp): replace

Merge changes I366740a9,I533abdd6,I6aa3b6dc into integration

* changes:
fix(n1sdp): mapping Run-time UART to IOFPGA UART0
fix(n1sdp): add numa node id for pcie controllers
fix(n1sdp): replace non-inclusive terms from dts file

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fix(n1sdp): mapping Run-time UART to IOFPGA UART0

Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UA

fix(n1sdp): mapping Run-time UART to IOFPGA UART0

Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UART0 for exclusiveness among the usage of the UARTs.

Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Change-Id: I366740a971a880decf0d373e9055e7ebda5df53a

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Merge "(feat)n1sdp: add support for OP-TEE SPMC" into integration

(feat)n1sdp: add support for OP-TEE SPMC

These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.

Signed-off-by: Vishnu Banavath <vishnu.banavath@

(feat)n1sdp: add support for OP-TEE SPMC

These changes are to add support for loading and booting
OP-TEE as SPMC running at SEL1 for N1SDP platform.

Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I0514db646d4868b6f0c56f1ea60495cb3f7364fd

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Merge changes I2fcf13b7,I153ccb43 into integration

* changes:
feat(n1sdp): add support for nt_fw_config
feat(n1sdp): enable trusted board boot on n1sdp

feat(n1sdp): enable trusted board boot on n1sdp

Move from RESET_TO_BL31 boot to a TBBR style boot on N1sdp.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I153ccb43a4a013830973c7a183825d62b372c65e

Merge changes from topics "rddaniel", "rdn1edge_dual" into integration

* changes:
plat/arm: add board support for rd-daniel platform
plat/arm/sgi: move GIC related constants to board files
pla

Merge changes from topics "rddaniel", "rdn1edge_dual" into integration

* changes:
plat/arm: add board support for rd-daniel platform
plat/arm/sgi: move GIC related constants to board files
platform/arm/sgi: add multi-chip mode parameter in HW_CONFIG dts
board/rdn1edge: add support for dual-chip configuration
drivers/arm/scmi: allow use of multiple SCMI channels
drivers/mhu: derive doorbell base address
plat/arm/sgi: include AFF3 affinity in core position calculation
plat/arm/sgi: add macros for remote chip device region
plat/arm/sgi: add chip_id and multi_chip_mode to platform variant info
plat/arm/sgi: move bl31_platform_setup to board file

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drivers/arm/scmi: allow use of multiple SCMI channels

On systems that have multiple platform components that can interpret the
SCMI messages, there is a need to support multiple SCMI channels (one
e

drivers/arm/scmi: allow use of multiple SCMI channels

On systems that have multiple platform components that can interpret the
SCMI messages, there is a need to support multiple SCMI channels (one
each to those platform components). Extend the existing SCMI interface
that currently supports only a single SCMI channel to support multiple
SCMI channels.

Change-Id: Ice4062475b903aef3b5e5bc37df364c9778a62c5
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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drivers/mhu: derive doorbell base address

In order to allow the MHUv2 driver to be usable with multiple MHUv2
controllers, use the base address of the controller from the platform
information instea

drivers/mhu: derive doorbell base address

In order to allow the MHUv2 driver to be usable with multiple MHUv2
controllers, use the base address of the controller from the platform
information instead of the MHUV2_BASE_ADDR macro.

Change-Id: I4dbab87b929fb0568935e6c8b339ce67937f8cd1
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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Merge changes I75799fd4,I4781dc6a into integration

* changes:
n1sdp: update platform macros for dual-chip setup
n1sdp: introduce platform information SDS region

n1sdp: update platform macros for dual-chip setup

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link for now only dual-chip is
supported.

n1sdp: update platform macros for dual-chip setup

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link for now only dual-chip is
supported.

A single instance of TF-A runs on master chip which should be aware of
slave chip's CPU and memory topology.

This patch updates platform macros to include remote chip's information
and also ensures that a single version of firmware works for both single
and dual-chip setup.

Change-Id: I75799fd46dc10527aa99585226099d836c21da70
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

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Merge "Switch AARCH32/AARCH64 to __aarch64__" into integration

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the cod

Switch AARCH32/AARCH64 to __aarch64__

NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.

All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)

Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Merge "n1sdp: add code for DDR ECC enablement and BL33 copy to DDR" into integration

n1sdp: add code for DDR ECC enablement and BL33 copy to DDR

N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
ena

n1sdp: add code for DDR ECC enablement and BL33 copy to DDR

N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
enabling the ECC bits in DMC620. Zeroing out several gigabytes of
memory from SCP is quite time consuming so functions are added that
zeros out the DDR memory from application processor which is
much faster compared to SCP. BL33 binary cannot be copied to DDR memory
before enabling ECC so this is also done by TF-A from IOFPGA-DDR3
memory to main DDR4 memory after ECC is enabled.

Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which
the entire DDR space cannot be accessed as DRAM2 starts in base
0x8080000000. So these macros are redefined for all ARM platforms.

Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

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Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration

* changes:
N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
N1SDP: Fix DRAM2 start address
Add option for defining platf

Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration

* changes:
N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
N1SDP: Fix DRAM2 start address
Add option for defining platform DRAM2 base
Disable speculative loads only if SSBS is supported

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N1SDP: Fix DRAM2 start address

The default DRAM2 start address for Arm platforms
is 0x880000000. However, for N1SDP platform this is
0x8080000000.

Fix the DRAM2 start address by initialising
PLAT_A

N1SDP: Fix DRAM2 start address

The default DRAM2 start address for Arm platforms
is 0x880000000. However, for N1SDP platform this is
0x8080000000.

Fix the DRAM2 start address by initialising
PLAT_ARM_DRAM2_BASE.

Without this fix there is a mismatch of the System
memory region view as seen by the BL31 runtime
firmware (PSCI) versus the view of the OS (which
is based on the description provided by UEFI. In
this case UEFI is correctly describing the DRAM2
start address).

This implicates in secondary cores failing to start
on some Operating Systems if the OS decides to place
the secondary start address in the mismatched region.

Change-Id: I57220e753219353dda429868b4c5e1a69944cc64
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>

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Merge changes from topic "aa-sbsa-watchdog" into integration

* changes:
plat/arm: introduce wrapper functions to setup secure watchdog
drivers/sbsa: add sbsa watchdog driver

plat/arm: introduce wrapper functions to setup secure watchdog

The BL1 stage setup code for ARM platforms sets up the SP805 watchdog
controller as the secure watchdog. But not all ARM platforms use

plat/arm: introduce wrapper functions to setup secure watchdog

The BL1 stage setup code for ARM platforms sets up the SP805 watchdog
controller as the secure watchdog. But not all ARM platforms use SP805
as the secure watchdog controller.

So introduce two new ARM platform code specific wrapper functions to
start and stop the secure watchdog. These functions then replace the
calls to SP805 driver in common BL1 setup code. All the ARM platforms
implement these wrapper functions by either calling into SP805 driver
or the SBSA watchdog driver.

Change-Id: I1a9a11b124cf3fac2a84f22ca40acd440a441257
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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