1 /*
2 * Copyright (c) 2013-2025, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <stddef.h>
9
10 #include <arch.h>
11 #include <arch_helpers.h>
12 #include <bl31/bl31.h>
13 #include <common/bl_common.h>
14 #include <common/debug.h>
15 #include <drivers/arm/cci.h>
16 #include <drivers/console.h>
17 #include <lib/mmio.h>
18 #include "mssr.h"
19 #include <plat/arm/common/plat_arm.h>
20 #include <plat/common/platform.h>
21 #include "ptp.h"
22 #include "pwrc.h"
23 #include "timer.h"
24
25 #include "rcar_def.h"
26 #include "rcar_private.h"
27 #include "rcar_version.h"
28
bl31_plat_get_next_image_ep_info(uint32_t type)29 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
30 {
31 bl2_to_bl31_params_mem_t *from_bl2 =
32 (bl2_to_bl31_params_mem_t *)PARAMS_BASE;
33 entry_point_info_t *next_image_info = (type == NON_SECURE) ?
34 &from_bl2->bl33_ep_info :
35 &from_bl2->bl32_ep_info;
36
37 return next_image_info->pc ? next_image_info : NULL;
38 }
39
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)40 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
41 u_register_t arg2, u_register_t arg3)
42 {
43 rcar_console_boot_init();
44
45 NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
46 }
47
bl31_plat_arch_setup(void)48 void bl31_plat_arch_setup(void)
49 {
50 static const uintptr_t BL31_RO_BASE = BL_CODE_BASE;
51 static const uintptr_t BL31_RO_LIMIT = BL_CODE_END;
52
53 rcar_configure_mmu_el3(BL31_BASE,
54 BL31_LIMIT - BL31_BASE,
55 BL31_RO_BASE, BL31_RO_LIMIT);
56
57 rcar_pwrc_code_copy_to_system_ram();
58 }
59
60 static const uintptr_t gicr_base_addrs[2] = {
61 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
62 0U /* Zero Termination */
63 };
64
bl31_platform_setup(void)65 void bl31_platform_setup(void)
66 {
67 /* Initialize generic timer */
68 u_register_t reg_cntfid = RCAR_CNTC_EXTAL;
69
70 rcar_mssr_setup();
71
72 /* Update memory mapped and register based frequency */
73 write_cntfrq_el0(reg_cntfid);
74 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF, reg_cntfid);
75
76 /* Enable the system level generic timer */
77 mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
78
79 gic_set_gicr_frames(gicr_base_addrs);
80
81 rcar_pwrc_setup();
82 rcar_ptp_setup();
83 }
84
85 const spd_pm_ops_t rcar_pm = {
86 .svc_migrate_info = rcar_pwrc_cpu_migrate_info,
87 };
88
bl31_plat_runtime_setup(void)89 void bl31_plat_runtime_setup(void)
90 {
91 psci_register_spd_pm_hook(&rcar_pm);
92
93 rcar_console_runtime_init();
94 console_switch_state(CONSOLE_FLAG_RUNTIME);
95 }
96