Merge "fix(arm): don't override the gic redistributor frames" into integration

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whet

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whether the platform might want to use something different. The thinking
was to provide a default and then let each platform override it, however
the order was swapped.

To fix this, put the gic_set_gicr_frames() in bl31_platform_setup()
rather than arm_bl31_platform_setup(). This way, platforms that use the
default can still enjoy it automatically pulled in from common code,
platforms that need fully custom gicr_frames can simply set it, and
platforms that override bl31_platform_setup() for unrelated reasons only
have to redo the call to gic_set_gicr_frames(). This has a tiny benefit
over the old approach in that there will never be 2 gicr_frames arrays.

Change-Id: I734737d3bd37ddbb3286abcdd92c88676c68cdc3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
ref

Merge changes I61d77211,I9cb5c1fa,I8e8a92fd into integration

* changes:
refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3
fix(gicv3): remove plat_gicv3_base.c
refactor(versal-net): use the generic GIC driver

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refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes

refactor(gicv3): clarify redistributor base address usage with USE_GIC_DRIVER=3

The GICv3 driver has 2 methods of discovering the redistributors:
a) via setting gicr_base - done at boot and assumes all GICR frames are
contiguous. This is the original method.

b) via gicv3_rdistif_probe() - called from platform code and requires
gicr_base == 0. It relaxes the requirement for frames to be
contiguous, like in a multichip configuration, and defers the
discovery to core bringup. This was introduced later.

Configurations possible with option a) are also possible with option b)
with only slightly different behaviour. USE_GIC_DRIVER=3 inherited
option b) from plat_gicv3_base.c and as such option a) is unusable.
However, it is unclear from code how this should be used. Clarify this
by requiring platforms initialise with gic_set_gicr_frames() and
adding relevant comments.

Also rename plat_arm_override_gicr_frames() to gic_set_gicr_frames() as
this is not plat arm specific and a part of the generic GIC driver.

Change-Id: I61d77211f8e65dc54cf9904069b500d26a06b5a5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add suppo

Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add support for local chip addressing

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feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version

feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version of routing table. This feature is activated when the
GICD_CFGID.LCA bit is set to 1.

The existing `gic600_multichip_data` data structure did not account for
the LCA feature. To support LCA:
- `rt_owner_base` is replaced by `base_addrs[]`. This is required
because each GICD in the system needs to be configured independently,
and their base addresses must be passed to the driver.
- `chip_addrs` is changed from 1D to 2D array to store the routing table
for each chip's GICD. The entries in `chip_addrs` are configuration
dependent, as the GIC specification does not enforce this.

On a multi-chip platform with chip count N where LCA is enabled by
default, the `gic600_multichip_data` structure should contain all copies
of the routing table (N*N entries). On platforms where LCA is not
supported, only the first sub-array with N entries is required. The
function signature of `gic600_multichip_init` remains unchanged, but if
the LCA feature is enabled, the driver will expect the routing table
configuration in the described format.

Change-Id: I8830c2cf90db6a0cae78e99914cd32c637284a2b
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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Merge changes from topic "DPE" into integration

* changes:
feat(tc): add RSS SDS region right after SCMI payload
refactor(n1sdp): update SDS driver calls
refactor(morello): update SDS driver c

Merge changes from topic "DPE" into integration

* changes:
feat(tc): add RSS SDS region right after SCMI payload
refactor(n1sdp): update SDS driver calls
refactor(morello): update SDS driver calls
refactor(juno): update SDS driver calls
refactor(sgi): update SDS driver calls
refactor(css): support multiple SDS regions

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refactor(n1sdp): update SDS driver calls

Update SDS driver calls to align with recent
changes [1] of the SDS driver.

- The driver now requires us to explicitly pass
the SDS region id to act on.
-

refactor(n1sdp): update SDS driver calls

Update SDS driver calls to align with recent
changes [1] of the SDS driver.

- The driver now requires us to explicitly pass
the SDS region id to act on.
- Implement plat_sds_get_regions() platform function
which is used by the driver to get SDS region
information per platform.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/24609/

Change-Id: I3447855fbe7427376d5f7aa0ba7356fe2f14d567
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>

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Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function

Merge changes I814cdadb,I429eb473,I441f9a60 into integration

* changes:
fix(n1sdp): fix spi_ids range for n1sdp multichip boot
fix(gicv3): move invocation of gicv3_get_multichip_base function
fix(gic600): fix gic600 maximum SPI ID

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fix(n1sdp): fix spi_ids range for n1sdp multichip boot

According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across bot

fix(n1sdp): fix spi_ids range for n1sdp multichip boot

According to GIC-600 TRM, it supports upto 960 SPIs.
This patch configures the SPI IDs range to 32-991, and distributes
them equally across both the chips.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I814cdadb59c8765c239ae0375e547718b7f208ff

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Merge changes I0a307cc1,Ic2ad5a56 into integration

* changes:
fix(morello): remove platform specific pwr_domain_suspend wrapper
fix(n1sdp): remove platform specific pwr_domain_suspend wrapper

fix(n1sdp): remove platform specific pwr_domain_suspend wrapper

Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platfor

fix(n1sdp): remove platform specific pwr_domain_suspend wrapper

Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platform specific
psci pwr_domain_suspend handler.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ic2ad5a561be29eee9229a5cc11aa3c9320a51cb7

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Merge "fix(n1sdp): add platform-specific power domain functions" into integration

Merge "fix(spmd): fix build error with spmd" into integration

fix(spmd): fix build error with spmd

Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0'
options, this causes a build failure as
'plat_spmd_handle_group0_interrupt' is called irrespective of

fix(spmd): fix build error with spmd

Currently when we build with 'SPD=spmd SPMD_SPM_AT_SEL2=0'
options, this causes a build failure as
'plat_spmd_handle_group0_interrupt' is called irrespective of
'SPMD_SPM_AT_SEL2' usage in 'spmd_group0_interrupt_handler_nwd'

So make 'plat_spmd_handle_group0_interrupt' dummy implementation
available just when spmd is enabled and SPMC_AT_EL3 is disabled.

Change-Id: Iaccd38faab81671c98f9165f318145187dca9bc2
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "mp/group0_support" into integration

* changes:
docs(spm): support for handling Group0 interrupts
feat(spmd): introduce platform handler for Group0 interrupt
feat(spmd

Merge changes from topic "mp/group0_support" into integration

* changes:
docs(spm): support for handling Group0 interrupts
feat(spmd): introduce platform handler for Group0 interrupt
feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABI
feat(spmd): register handler for group0 interrupt from NWd

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fix(n1sdp): add platform-specific power domain functions

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor
power off to resolve an error on N1SDP/Morello. Prior to this fix,
turn

fix(n1sdp): add platform-specific power domain functions

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf added a redistributor
power off to resolve an error on N1SDP/Morello. Prior to this fix,
turning off both cores in a cluster would cause a hang when powering
back on either core. This change introduced issues on other platforms
with a different GIC implementation, and was reverted in commit
60719e4e0965aead49d927f12bf2a37bd2629012.

This commit uses the previous fix in platform-specific implementations
of power domain off/suspend functions.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I52c463646c494fe931ff4ce47afb940a56978fcd

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feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder fo

feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder for future Group0 interrupt sources.

Moreover, this patch also provides a dummy implementation of the
above mentioned platform hook for QEMU, corstone100, n1sdp and
hikey960 ports.

Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4" into integration

fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4

The purpose of this patch is to address the T241 erratum T241-FABRIC-4,
which causes unexpected behavior in the GIC when multiple transactions

fix(gicv3): workaround for NVIDIA erratum T241-FABRIC-4

The purpose of this patch is to address the T241 erratum T241-FABRIC-4,
which causes unexpected behavior in the GIC when multiple transactions
are received simultaneously from different sources. This hardware issue
impacts NVIDIA server platforms that use more than two T241 chips
interconnected. Each chip has support for 320 {E}SPIs.

This issue occurs when multiple packets from different GICs are
incorrectly interleaved at the target chip. The erratum text below
specifies exactly what can cause multiple transfer packets susceptible
to interleaving and GIC state corruption. GIC state corruption can
lead to a range of problems, including kernel panics, and unexpected
behavior.

Erratum documentation:
https://developer.nvidia.com/docs/t241-fabric-4/nvidia-t241-fabric-4-errata.pdf

The workaround is to ensure that MMIO accesses target the GIC on the
socket that holds the data, for example SPI ranges owned by the socket’s
GIC. This ensures that the GIC will not utilize the inter-socket AXI
Stream interface for servicing these GIC MMIO accesses.

This patch updates the functions that use the GICD_In{E} registers to
ensure that the accesses are directed to the chip that owns the SPI,
instead of using the global alias.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I04e33ba64eb306bd5fdabb56e63cbe273d8cd632

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Merge changes from topic "tonnad01/gcc_warn_fix" into integration

* changes:
fix(scmi): change function prototype to fix gcc error
fix(rdn1edge): change variable type to fix gcc sign conversion

Merge changes from topic "tonnad01/gcc_warn_fix" into integration

* changes:
fix(scmi): change function prototype to fix gcc error
fix(rdn1edge): change variable type to fix gcc sign conversion error

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fix(scmi): change function prototype to fix gcc error

Change function prototype of plat_css_get_scmi_info() to fix the GCC
sign conversion error "comparison between signed and unsigned integer
expre

fix(scmi): change function prototype to fix gcc error

Change function prototype of plat_css_get_scmi_info() to fix the GCC
sign conversion error "comparison between signed and unsigned integer
expressions". Changing channel_id type to unsigned int since it can
never be a negative value.

Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I579b21497329db40897c10d86c8fc68e4877f3db

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Merge changes I2fcf13b7,I153ccb43 into integration

* changes:
feat(n1sdp): add support for nt_fw_config
feat(n1sdp): enable trusted board boot on n1sdp

feat(n1sdp): add support for nt_fw_config

This patch adds support to load nt_fw_config with the information from
plat_info sds structure which is then passed from BL2 to BL33.

Signed-off-by: sahil

feat(n1sdp): add support for nt_fw_config

This patch adds support to load nt_fw_config with the information from
plat_info sds structure which is then passed from BL2 to BL33.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I2fcf13b7bf5ab042ef830157fd9cceedbdca617a

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feat(n1sdp): enable trusted board boot on n1sdp

Move from RESET_TO_BL31 boot to a TBBR style boot on N1sdp.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I153ccb43a4a013830973c7a183825d62b372c65e