| /rk3399_ARM-atf/plat/mediatek/mt8192/ |
| H A D | plat_topology.c | 47 if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { in plat_core_pos_by_mpidr()
60 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/mediatek/mt8195/ |
| H A D | plat_topology.c | 42 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { in plat_core_pos_by_mpidr()
55 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/renesas/rcar_gen4/ |
| H A D | plat_topology.c | 33 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) in plat_core_pos_by_mpidr()
48 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) in rcar_cluster_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/mediatek/mt8186/ |
| H A D | plat_topology.c | 42 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) { in plat_core_pos_by_mpidr()
55 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/arm/common/ |
| H A D | arm_topology.c | 31 pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
36 cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) & in arm_check_mpidr()
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| /rk3399_ARM-atf/plat/renesas/rcar_gen5/ |
| H A D | plat_topology.c | 78 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0U) { in plat_core_pos_by_mpidr()
95 if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0U) { in rcar_cluster_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/amlogic/common/ |
| H A D | aml_topology.c | 44 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/arm/board/a5ds/ |
| H A D | a5ds_topology.c | 39 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/qemu/common/ |
| H A D | topology.c | 48 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/aspeed/ast2700/ |
| H A D | plat_topology.c | 32 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/ |
| H A D | hikey960_topology.c | 53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_topology.c | 53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/mediatek/mt8173/ |
| H A D | plat_topology.c | 47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/mediatek/mt8183/ |
| H A D | plat_topology.c | 46 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/st/stm32mp2/ |
| H A D | stm32mp2_topology.c | 42 cpu_id = (mpidr_copy >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/st/stm32mp1/ |
| H A D | stm32mp1_topology.c | 42 cpu_id = (mpidr_copy >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/socionext/synquacer/ |
| H A D | sq_topology.c | 23 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/socionext/uniphier/ |
| H A D | uniphier_topology.c | 35 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/renesas/common/ |
| H A D | plat_topology.c | 34 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/qemu/qemu_sbsa/ |
| H A D | sbsa_topology.c | 50 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rd1ae/include/ |
| H A D | rd1ae_helpers.S | 32 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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| /rk3399_ARM-atf/plat/arm/board/morello/aarch64/ |
| H A D | morello_helper.S | 42 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/include/ |
| H A D | socfpga_plat_def.h | 19 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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| /rk3399_ARM-atf/plat/arm/board/n1sdp/aarch64/ |
| H A D | n1sdp_helper.S | 41 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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| /rk3399_ARM-atf/plat/intel/soc/n5x/include/ |
| H A D | socfpga_plat_def.h | 20 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
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