1f85f37d4SNina Wu /* 2f85f37d4SNina Wu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3f85f37d4SNina Wu * 4f85f37d4SNina Wu * SPDX-License-Identifier: BSD-3-Clause 5f85f37d4SNina Wu */ 6f85f37d4SNina Wu 7f85f37d4SNina Wu /* Project Includes */ 8f85f37d4SNina Wu #include <arch.h> 9f85f37d4SNina Wu #include <arch_helpers.h> 10f85f37d4SNina Wu #include <lib/psci/psci.h> 11f85f37d4SNina Wu 12f85f37d4SNina Wu /* Platform Includes */ 13f85f37d4SNina Wu #include <plat_helpers.h> 14f85f37d4SNina Wu #include <platform_def.h> 15f85f37d4SNina Wu 16f85f37d4SNina Wu const unsigned char mtk_power_domain_tree_desc[] = { 17f85f37d4SNina Wu /* Number of root nodes */ 18f85f37d4SNina Wu PLATFORM_SYSTEM_COUNT, 19f85f37d4SNina Wu /* Number of children for the root node */ 20*82c00c2fSJames Liao PLATFORM_MCUSYS_COUNT, 21*82c00c2fSJames Liao /* Number of children for the mcusys node */ 22f85f37d4SNina Wu PLATFORM_CLUSTER_COUNT, 23f85f37d4SNina Wu /* Number of children for the first cluster node */ 24f85f37d4SNina Wu PLATFORM_CLUSTER0_CORE_COUNT, 25f85f37d4SNina Wu }; 26f85f37d4SNina Wu 27f85f37d4SNina Wu /******************************************************************************* 28f85f37d4SNina Wu * This function returns the MT8192 default topology tree information. 29f85f37d4SNina Wu ******************************************************************************/ plat_get_power_domain_tree_desc(void)30f85f37d4SNina Wuconst unsigned char *plat_get_power_domain_tree_desc(void) 31f85f37d4SNina Wu { 32f85f37d4SNina Wu return mtk_power_domain_tree_desc; 33f85f37d4SNina Wu } 34f85f37d4SNina Wu 35f85f37d4SNina Wu /******************************************************************************* 36f85f37d4SNina Wu * This function implements a part of the critical interface between the psci 37f85f37d4SNina Wu * generic layer and the platform that allows the former to query the platform 38f85f37d4SNina Wu * to convert an MPIDR to a unique linear index. An error code (-1) is returned 39f85f37d4SNina Wu * in case the MPIDR is invalid. 40f85f37d4SNina Wu ******************************************************************************/ plat_core_pos_by_mpidr(u_register_t mpidr)41f85f37d4SNina Wuint plat_core_pos_by_mpidr(u_register_t mpidr) 42f85f37d4SNina Wu { 43f85f37d4SNina Wu unsigned int cluster_id, cpu_id; 44f85f37d4SNina Wu 45f85f37d4SNina Wu if (read_mpidr() & MPIDR_MT_MASK) { 46f85f37d4SNina Wu /* ARMv8.2 arch */ 47f85f37d4SNina Wu if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { 48f85f37d4SNina Wu return -1; 49f85f37d4SNina Wu } 50f85f37d4SNina Wu return plat_mediatek_calc_core_pos(mpidr); 51f85f37d4SNina Wu } 52f85f37d4SNina Wu 53f85f37d4SNina Wu mpidr &= MPIDR_AFFINITY_MASK; 54f85f37d4SNina Wu 55f85f37d4SNina Wu if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { 56f85f37d4SNina Wu return -1; 57f85f37d4SNina Wu } 58f85f37d4SNina Wu 59f85f37d4SNina Wu cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 60f85f37d4SNina Wu cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 61f85f37d4SNina Wu 62f85f37d4SNina Wu if (cluster_id >= PLATFORM_CLUSTER_COUNT) { 63f85f37d4SNina Wu return -1; 64f85f37d4SNina Wu } 65f85f37d4SNina Wu 66f85f37d4SNina Wu /* 67f85f37d4SNina Wu * Validate cpu_id by checking whether it represents a CPU in 68f85f37d4SNina Wu * one of the two clusters present on the platform. 69f85f37d4SNina Wu */ 70f85f37d4SNina Wu if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { 71f85f37d4SNina Wu return -1; 72f85f37d4SNina Wu } 73f85f37d4SNina Wu 74f85f37d4SNina Wu return (cpu_id + (cluster_id * 8)); 75f85f37d4SNina Wu } 76